MPC8280 datasheet(147/1386 Pages) FREESCALE

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Memory Map

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

3-3

0x10048

Local bus transfer error status control register 1 (L_TESCR1) R/W

32 bits

0x0000_0000

4.3.2.12/4-42

0x1004C

Local bus transfer error status control register 2 (L_TESCR2) R/W

32 bits

0x0000_0000

4.3.2.13/4-43

0x10050

60x bus DMA transfer error address (PDTEA)

32 bits

undefined

19.2.3/19-4

0x10054

60x bus DMA transfer error MSNUM (PDTEM)

8 bits

undefined

19.2.4/19-4

0x10055

Reserved

—

24 bits

—

0x10058

Local bus DMA transfer error address (LDTEA)

32 bits

undefined

19.2.3/19-4

0x1005C

Local bus DMA transfer error MSNUM (LDTEM)

8 bits

undefined

19.2.4/19-4

0x1005D–

0x100FF

Reserved

—

163

bytes

——

Memory Controller

0x10100

Base register bank 0 (BR0)

R/W

32 bits

see

Figure 11-6

11.3.1/11-13

0x10104

Option register bank 0 (OR0)

R/W

32 bits

0xFE00_0EF4

11.3.2/11-15

0x10108

Base register bank 1 (BR1)

R/W

32 bits

0x0000_0000

11.3.1/11-13

0x1010C

Option register bank 1 (OR1)

R/W

32 bits

undefined

11.3.2/11-15

0x10110

Base register bank 2 (BR2)

R/W

32 bits

0x0000_0000

11.3.1/11-13

0x10114

Option register bank 2 (OR2)

R/W

32 bits

undefined

11.3.2/11-15

0x10118

Base register bank 3 (BR3)

R/W

32 bits

0x0000_0000

11.3.1/11-13

0x1011C

Option register bank 3 (OR3)

R/W

32 bits

undefined

11.3.2/11-15

0x10120

Base register bank 4 (BR4)

R/W

32 bits

0x0000_0000

11.3.1/11-13

0x10124

Option register bank 4 (OR4)

R/W

32 bits

undefined

11.3.2/11-15

0x10128

Base register bank 5 (BR5)

R/W

32 bits

0x0000_0000

11.3.1/11-13

0x1012C

Option register bank 5 (OR5)

R/W

32 bits

undefined

11.3.2/11-15

0x10130

Base register bank 6 (BR6)

R/W

32 bits

0x0000_0000

11.3.1/11-13

0x10134

Option register bank 6 (OR6)

R/W

32 bits

undefined

11.3.2/11-15

0x10138

Base register bank 7 (BR7)

R/W

32 bits

0x0000_0000

11.3.1/11-13

0x1013C

Option register bank 7 (OR7)

R/W

32 bits

undefined

11.3.2/11-15

0x10140

Base register bank 8 (BR8)

R/W

32 bits

0x0000_0000

11.3.1/11-13

0x10144

Option register bank 8 (OR8)

R/W

32 bits

undefined

11.3.2/11-15

0x10148

Base register bank 9 (BR9)

R/W

32 bits

0x0000_0000

11.3.1/11-13

0x1014C

Option register bank 9 (OR9)

R/W

32 bits

undefined

11.3.2/11-15

0x10150

Base register bank 10 (BR10)

R/W

32 bits

0x0000_0000

11.3.1/11-13

0x10154

Option register bank 10 (OR10)

R/W

32 bits

undefined

11.3.2/11-15

Table 3-1. Internal Memory Map (continued)

Address

(offset)

R/W

Size

Reset

Section/Page

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