MPC8280 datasheet(150/1386 Pages) FREESCALE

150 / 1386 page

Memory Map

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

3-6

Freescale Semiconductor

0x104C0

Outbound free_FIFO head pointer register (OFHPR)

R/W

32 bits

0x0000_0000

9.12.3.3.1/9-75

0x104C8

Outbound free_FIFO tail pointer register (OFTPR)

R/W

32 bits

0x0000_0000

9.12.3.3.1/9-75

0x104D0

Outbound post_FIFO head pointer register (OPHPR)

R/W

32 bits

0x0000_0000

9.12.3.3.2/9-76

0x104D8

Outbound post_FIFO tail pointer register (OPTPR)

R/W

32 bits

0x0000_0000

9.12.3.3.2/9-76

0x104E4

Message unit control register (MUCR)

R/W

32 bits

0x0000_0002

9.12.3.4.7/9-84

0x104F0

Queue base address register (QBAR)

R/W

32 bits

0x0000_0000

9.12.3.4.8/9-85

0x10500

DMA 0 mode register (DMAMR0)

R/W

32 bits

0x0000_0000

9.13.1.6.1/9-89

0x10504

DMA 0 status register (DMASR0)

R/W

32 bits

0x0000_0000

9.13.1.6.2/9-91

0x10508

DMA 0 current descriptor address register (DMACDAR0)

R/W

32 bits

0x0000_0000

9.13.1.6.3/9-92

0x10510

DMA 0 source address register (DMASAR0)

R/W

32 bits

0x0000_0000

9.13.1.6.4/9-93

0x10518

DMA 0 destination address register (DMADAR0)

R/W

32 bits

0x0000_0000

9.13.1.6.5/9-94

0x10520

DMA 0 byte count register (DMABCR0)

R/W

32 bits

0x0000_0000

9.13.1.6.6/9-94

0x10524

DMA 0 next descriptor address register (DMANDAR0)

R/W

32 bits

0x0000_0000

9.13.1.6.7/9-95

0x10580

DMA 1 mode register (DMAMR1)

R/W

32 bits

0x0000_0000

9.13.1.6.1/9-89

0x10584

DMA 1 status register (DMASR1)

R/W

32 bits

0x0000_0000

9.13.1.6.2/9-91

0x10588

DMA 1 current descriptor address register (DMACDAR1)

R/W

32 bits

0x0000_0000

9.13.1.6.3/9-92

0x10590

DMA 1 source address register (DMASAR1)

R/W

32 bits

0x0000_0000

9.13.1.6.4/9-93

0x10598

DMA 1 destination address register (DMADAR1)

R/W

32 bits

0x0000_0000

9.13.1.6.5/9-94

0x105A0

DMA 1 byte count register (DMABCR1)

R/W

32 bits

0x0000_0000

9.13.1.6.6/9-94

0x105A4

DMA 1 next descriptor address register (DMANDAR1)

R/W

32 bits

0x0000_0000

9.13.1.6.7/9-95

0x10600

DMA 2 mode register (DMAMR2)

R/W

32 bits

0x0000_0000

9.13.1.6.1/9-89

0x10604

DMA 2 status register (DMASR2)

R/W

32 bits

0x0000_0000

9.13.1.6.2/9-91

0x10608

DMA 2 current descriptor address register (DMACDAR2)

R/W

32 bits

0x0000_0000

9.13.1.6.3/9-92

0x10610

DMA 2 source address register (DMASAR2)

R/W

32 bits

0x0000_0000

9.13.1.6.4/9-93

0x10618

DMA 2 destination address register (DAR2)

R/W

32 bits

0x0000_0000

9.13.1.6.5/9-94

0x10620

DMA 2 byte count register (DMABCR2)

R/W

32 bits

0x0000_0000

9.13.1.6.6/9-94

0x10624

DMA 2 next descriptor address register (DMANDAR2)

R/W

32 bits

0x0000_0000

9.13.1.6.7/9-95

0x10680

DMA 3 mode register (DMAMR3)

R/W

32 bits

0x0000_0000

9.13.1.6.1/9-89

0x10684

DMA 3 status register (DMASR3)

R/W

32 bits

0x0000_0000

9.13.1.6.2/9-91

0x10688

DMA 3 current descriptor address register (DMACDAR3)

R/W

32 bits

0x0000_0000

9.13.1.6.3/9-92

0x10690

DMA 3 source address register (DMASAR3)

R/W

32 bits

0x0000_0000

9.13.1.6.4/9-93

0x10698

DMA 3 destination address register (DMADAR3)

R/W

32 bits

0x0000_0000

9.13.1.6.5/9-94

Table 3-1. Internal Memory Map (continued)

Address

(offset)

R/W

Size

Reset

Section/Page

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