MPC8280 datasheet(143/1386 Pages) FREESCALE

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G2_LE Core

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

2-27

round-convert. The LSU has two pipeline stages. The first stage is for effective address calculation

and MMU translation, and the second is for accessing data in the cache.

•

The complete/write-back pipeline stage maintains the correct architectural machine state and

transfers the contents of the rename registers to the GPRs and FPRs as instructions are retired. If

the completion logic detects an instruction causing an exception, all following instructions are

canceled, their execution results in rename registers are discarded, and instructions are fetched

from the correct instruction stream.

A superscalar processor core issues multiple independent instructions into multiple pipelines allowing

instructions to execute in parallel. The G2_LE core has five independent execution units, one each for

integer instructions, floating-point instructions, branch instructions, load/store instructions, and system

(GPRs and FPRs, respectively), allowing integer and floating-point calculations to occur simultaneously

without interference. Integer division performance of the G2_LE core has been improved, with the divwux

and divwx instructions executing in 20 clock cycles instead of the 37 cycles required in the MPC603e.

The core provides support for single-cycle store and an adder/comparator in the system register unit that

allows the dispatch and execution of multiple integer add and compare instructions on each cycle.

Because the PowerPC architecture can be applied to such a wide variety of implementations, instruction

timing among processor cores varies accordingly.

2.8

Differences Between the MPC8280 G2_LE

Embedded Core and the MPC603e

The G2_LE processor core is a derivative of the MPC603e microprocessor design. Some changes have

been made and are visible either to a programmer or a system designer. Any software designed around an

MPC603e is functional when replaced with the G2_LE except for the specific customer-visible changes

listed in Table 2-6.

Software can distinguish between the MPC603e and the G2_LE by reading the processor version register

(PVR). The G2_LE processor version number is 0x0081; the processor revision level starts at 0x0100 and

is incremented for each revision of the chip.

Table 2-6. Differences Between G2_LE Core and MPC603e

Description

Impact

An additional input interrupt signal, CINT,

implements a critical interrupt function.

MSR[CE] is allocated for enabling the critical interrupt

A new instruction is implemented for

critical interrupt

Return from Critical Interrupt (rfci) is implemented to return from these exception

handlers

Vector offset for critical interrupt

An exception vector offset of 0x00A00 is defined for critical interrupt

Two new registers are implemented for

saving processor state for critical

interrupts

CSRR0 and CSRR1 have the same bit assignments as SRR0 and SRR1,

respectively.

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