MPC8280 datasheet(149/1386 Pages) FREESCALE

149 / 1386 page

Memory Map

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

3-5

System Integration Timers

0x10200–

0x10 21F

Reserved

—

32 bytes

—

0x10220

Time counter status and control register (TMCNTSC)

R/W

16 bits

0x0000

4.3.2.14/4-43

0x10224

Time counter register (TMCNT)

R/W

32 bits

0x0000_0000

4.3.2.15/4-44

0x10228

Reserved

—

32 bits

—

0x1022C

Time counter alarm register (TMCNTAL)

R/W

32 bits

0x0000_0000

4.3.2.16/4-45

0x10230–

0x1023F

Reserved

—

16 bytes

—

0x10240

Periodic interrupt status and control register (PISCR)

R/W

16 bits

0x0000

4.3.3.1/4-46

0x10244

Periodic interrupt count register (PITC)

R/W

32 bits

0x0000_0000

4.3.3.2/4-47

0x10248

Periodic interrupt timer register (PITR)

32 bits

0x0000_0000

4.3.3.3/4-48

0x1024C–

0x102A8

Reserved

—

92 bytes

—

0x102AA–

0x1042F

Reserved

—

372

bytes

——

PCI

0x10430

Outbound interrupt status register (OMISR)

R/W

32 bits

0x0000_0000

9.12.3.4.3/9-80

0x10434

Outbound interrupt mask register (OMIMR)

R/W

32 bits

0x0000_0000

9.12.3.4.4/9-81

0x10440

Inbound FIFO queue port register (IFQPR)

R/W

32 bits

0x0000_0000

9.12.3.4.1/9-78

0x10444

Outbound FIFO queue port register (OFQPR)

R/W

32 bits

0x0000_0000

9.12.3.4.2/9-79

0x10450

Inbound message register 0 (IMR0)

R/W

32 bits

undefined

9.12.1.1/9-67

0x10454

Inbound message register 1 (IMR1)

R/W

32 bits

undefined

9.12.1.1/9-67

0x10458

Outbound message register 0 (OMR0)

R/W

32 bits

undefined

9.12.1.2/9-67

0x1045C

Outbound message register 1 (OMR1)

R/W

32 bits

undefined

9.12.1.2/9-67

0x10460

Outbound doorbell register (ODR)

R/W

32 bits

0x0000_0000

9.12.2.1/9-68

0x10468

Inbound doorbell register (IDR)

R/W

32 bits

0x0000_0000

9.12.2.2/9-69

0x10480

Inbound message interrupt status register (IMISR)

R/W

32 bits

0x0000_0000

9.12.3.4.5/9-82

0x10484

Inbound message interrupt mask register (IMIMR)

R/W

32 bits

0x0000_0000

9.12.3.4.6/9-83

0x104A0

Inbound free_FIFO head pointer register (IFHPR)

R/W

32 bits

0x0000_0000

9.12.3.2.1/9-72

0x104A8

Inbound free_FIFO tail pointer register (IFTPR)

R/W

32 bits

0x0000_0000

9.12.3.2.1/9-72

0x104B0

Inbound post_FIFO head pointer register (IPHPR)

R/W

32 bits

0x0000_0000

9.12.3.2.2/9-73

0x104B8

Inbound post_FIFO tail pointer register (IPTPR)

R/W

32 bits

0x0000_0000

9.12.3.2.2/9-73

Table 3-1. Internal Memory Map (continued)

Address

(offset)

R/W

Size

Reset

Section/Page

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