MPC8280 datasheet(151/1386 Pages) FREESCALE

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Memory Map

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

3-7

0x106A0

DMA 3 byte count register (DMABCR3)

R/W

32 bits

0x0000_0000

9.13.1.6.6/9-94

0x106A4

DMA 3 next descriptor address register (DMANDAR3)

R/W

32 bits

0x0000_0000

9.13.1.6.7/9-95

0x10800

PCI outbound translation address register 0 (POTAR0)

R/W

32 bits

0x0000_0000

9.11.1.3/9-30

0x10808

PCI outbound base address register 0 (POBAR0)

R/W

32 bits

0x0000_0000

9.11.1.4/9-31

0x10810

PCI outbound comparison mask register 0 (POCMR0)

R/W

32 bits

0x0000_0000

9.11.1.5/9-32

0x10818

PCI outbound translation address register 1 (POTAR1)

R/W

32 bits

0x0000_0000

9.11.1.3/9-30

0x10820

PCI outbound base address register 1 (POBAR1)

R/W

32 bits

0x0000_0000

9.11.1.4/9-31

0x10828

PCI outbound comparison mask register 1 (POCMR1)

R/W

32 bits

0x0000_0000

9.11.1.5/9-32

0x10830

PCI outbound translation address register 2 (POTAR2)

R/W

32 bits

0x0000_0000

9.11.1.3/9-30

0x10838

PCI outbound base address register 2 (POBAR2)

R/W

32 bits

0x0000_0000

9.11.1.4/9-31

0x10840

PCI outbound comparison mask register 2 (POCMR2)

R/W

32 bits

0x0000_0000

9.11.1.5/9-32

0x10878

Discard timer control register (PTCR)

R/W

32 bits

0x0000_0000

9.11.1.6/9-33

0x1087C

General purpose control register (GPCR)

R/W

32 bits

0x0000_0000

9.11.1.7/9-33

0x10880

PCI general control register (PCI_GCR)

R/W

32 bits

0x0000_0000

9.11.1.8/9-35

0x10884

Error status register (ESR)

R/W

32 bits

0x0000_0000

9.11.1.9/9-35

0x10888

Error mask register (EMR)

R/W

32 bits

0x0000_0FFF

9.11.1.10/9-37

0x1088C

Error control register (ECR)

R/W

32 bits

0x0000_00FF

9.11.1.11/9-38

0x10890

PCI error address capture register (PCI_EACR)

R/W

32 bits

0x0000_0000

9.11.1.12/9-39

0x10898

PCI error data capture register (PCI_EDCR)

R/W

32 bits

0x0000_0000

9.11.1.13/9-40

0x108A0

PCI error control capture register (PCI_ECCR)

R/W

32 bits

0x0000_0000

9.11.1.14/9-40

0x108D0

PCI inbound translation address register 1 (PITAR1)

R/W

32 bits

0x0000_0000

9.11.1.15/9-42

0x108D8

PCI inbound base address register 1 (PIBAR1)

R/W

32 bits

0x0000_0000

9.11.1.16/9-42

0x108E0

PCI inbound comparison mask register 1 (PICMR1)

R/W

32 bits

0x0000_0000

9.11.1.17/9-43

0x108E8

PCI inbound translation address register 0 (PITAR0)

R/W

32 bits

0x0000_0000

9.11.1.15/9-42

0x108F0

PCI inbound base address register 0 (PIBAR0)

R/W

32 bits

0x0000_0000

9.11.1.16/9-42

0x108F8

PCI inbound comparison mask register 0 (PICMR0)

R/W

32 bits

0x0000_0000

9.11.1.17/9-43

0x10900

PCI CFG_ADDR

R/W

32 bits

undefined

9.9.1.4.4/9-15

0x10904

PCI CFG_DATA

R/W

32 bits

0x0000_0000

9.9.1.4.4/9-15

0x10908

PCI INT_AC

R/W

32 bits

undefined

9.9.1.4.7/9-17

Interrupt Controller

0x10C00

SIU interrupt configuration register (SICR)

R/W

16 bits

0x0000

4.3.1.1/4-17

0x10C02

Reserved

—

16 bits

—

Table 3-1. Internal Memory Map (continued)

Address

(offset)

R/W

Size

Reset

Section/Page

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