MPC8280 datasheet(144/1386 Pages) FREESCALE

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G2_LE Core

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

2-28

Freescale Semiconductor

Supports instruction and data cache

way-locking in addition to entire instruction

and data cache locking

Implements a cache way locking mechanism for both the instruction and data

caches. One to three of the four ways in the cache can be locked with control bits

in the HID2 register. See Section 2.3.1.2.3, “Hardware

Implementation-Dependent Register 2 (HID2).”

Four additional SPRG registers

The additional SPRGs reduce latencies that may be incurred from saving

registers to memory while in an exception handler

One new address breakpoint register

IABR2

Instruction address breakpoint exceptions in both the MPC603e and the G2_LE

cores use the 0x01300 vector offset

Two new data address breakpoint

registers are implemented in the G2_LE

The two new data address breakpoint registers (DABR and DABR2) expand the

debug functionality of the breakpoints. The new breakpoint registers are

accessible as SPRs with mtspr and mfspr.

One instruction register and one data

breakpoint control register are

implemented

IBCR and DBCR are implemented to support the additional debug features.

These registers are accessible as SPRs with mtspr and mfspr.

Vector offset for data address breakpoint

exception is 0x00300

Data address breakpoint exception is a DSI exception. The cause of a DSI

exception can be determined by the bit settings of DSISR[9]. DAR contains the

address of the breakpoint match condition.

One new register is implemented for

supporting system level memory map

System memory base address register (MBAR) can be accessed with mtspr or

mfspr using SPR311 in supervisor mode. It can store the present memory base

address for the system memory map.

The G2_LE has eight pairs of data and

eight pairs of instruction BAT registers

IBAT4–IBAT7 are the four additional pairs of instruction BATs and DBAT4–DBAT7

are the four additional data BATs. HID2[HBE] is added for enabling or disabling

the four additional pairs of BAT registers. These BATs are accessible by the mfspr

and mtspr instructions regardless of the setting of HID2[HBE].

Added hardware support for misaligned

little endian accesses

Except for strings/multiples, little-endian load/store accesses not on a word

boundary generate exceptions under the same circumstances as big-endian

accesses.

Removed misalignment support for eciwx

and ecowx instructions

These instructions take an alignment exception if not on a word boundary.

Added ability to broadcast dcbf, dcbi, and

dcbst onto the 60x bus

Setting HID0[ABE] enables the new broadcast feature (new in the PID7v-603e).

The default is to not broadcast these operations.

Added ability to reflect the value of the M

bit onto the 60x bus during instruction

translations

Setting HID0[IFEM] enables this feature. The default is to not present the M bit on

the bus.

Removed HID0[EICE]

There is no support for ICE pipeline tracking.

Added pin-configurable reset vector

The value of MSR[IP], interrupt prefix, is determined at hard reset by the hardware

configuration word.

Addition of speed-for-power functionality

The processor core implements an additional dynamic power management

mechanism. HID2[SFP] controls this function. See Section 2.3.1.2.3, “Hardware

Implementation-Dependent Register 2 (HID2).”

Table 2-6. Differences Between G2_LE Core and MPC603e (continued)

Description

Impact

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