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Reset

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

5-6

Freescale Semiconductor

Table 5-4 describes RMR fields.

5.4

Reset Configuration

Various features may be configured during hard reset or power-on reset. For example, one configurable

features is core disable, which can be used to configure a system that uses two MPC8280s, one a slave

device and the other a the host with an active core. Most configurable features are reconfigured whenever

HRESET is asserted. However, the clock mode is configured only when PORESET is asserted.

The 32-bit hard reset configuration word is described in Section 5.4.1, “Hard Reset Configuration Word.”

The reset configuration sequence is designed to support a system that uses up to eight MPC8280 chips,

each configured differently. It needs no additional glue logic for reset configuration.

The description below explains the operation of this sequence with regard to a multiple-MPC8280 system.

This and other simpler systems are described in Section 5.4.2, “Hard Reset Configuration Examples.” In

a typical multi-MPC8280 system, one MPC8280 should act as the configuration master while all other

MPC8280s should act as configuration slaves. The configuration master in the system typically reads the

various configuration words from EPROM in the system and uses them to configure itself as well as the

configuration slaves. How the MPC8280 acts during reset configuration is determined by the value of the

RSTCONF input while PORESET changes from assertion to negation. If RSTCONF is asserted while

PORESET changes, MPC8280 is a configuration master; otherwise, it is a slave.

In a typical multiple-MPC8280 system, RSTCONF input of the configuration master should be hard wired

to ground, while RSTCONF inputs of other chips should be connected to the high-order address bits of the

configuration master, as described in Table 5-5.

Table 5-4. RMR Field Descriptions

Bits

Name

Function

0–30

—

Reserved, should be cleared.

CSRE

Checkstop reset enable. The core can enter checkstop mode as the result of several exception

conditions. Setting CSRE configures the chip to perform a hard reset sequence whenever the core

enters checkstop state.

0 Reset not generated when core enters checkstop state.

1 Reset generated when core enters checkstop state.

Note: When the core is disabled, CSRE must be cleared.

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