MPC8280 datasheet(232/1386 Pages) FREESCALE

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Reset

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

5-8

Freescale Semiconductor

In a simple system that uses one stand-alone MPC8280, it is possible to use the default hard reset

configuration word (all zeros). This is done by tying RSTCONF input to VCC. Another scenario may be

a system which has no boot EPROM. In this case the user can configure the MPC8280 as a configuration

slave by driving RSTCONF to 1 during PORESET assertion and then applying a negative pulse on

RSTCONF and an appropriate configuration word on D[0–31]. In such a system, asserting HRESET in the

middle of operation causes the MPC8280 to return to the configuration programmed after PORESET

assertion (not the default configuration represented by configuration word of all zeros).

5.4.1

Hard Reset Configuration Word

The contents of the hard reset configuration word are shown in Figure 5-4.

Table 5-7 describes hard reset configuration word fields.

Field EARB EXMC CDIS EBM

BPS

CIP

ISPS

L2CPC

DPPC

PLLBP

ISB

Reset

0000_0000_0000_0000

Field

BMS

BBD

MMR

LBPC

APPC

CS10PC

ALD_EN

—

MODCK_H

Reset

0000_0000_0000_0000

Figure 5-4. Hard Reset Configuration Word

Table 5-7. Hard Reset Configuration Word Field Descriptions

Bits

Name

Description

EARB1

External arbitration. Defines the initial value for ACR[EARB]. If EARB = 1, external arbitration is

assumed. See Section 4.3.2.2, “60x Bus Arbiter Configuration Register (PPC_ACR).”

EXMC

External MEMC. Defines the initial value of BR0[EMEMC]. If EXMC = 1, an external memory

controller is assumed. See Section 11.3.1, “Base Registers (BRx).”

CDIS1

Core disable. Defines the initial value for the SIUMCR[CDIS].

0 The core is active. See Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR).”

1 The core is disabled. In this mode the MPC8280 functions as a slave.

EBM1

External bus mode. Defines the initial value of BCR[EBM]. See Section 4.3.2.1, “Bus

Configuration Register (BCR).”

4–5

BPS

Boot port size. Defines the initial value of BR0[PS], the port size for memory controller bank 0.

00 64-bit port size

01 8-bit port size

10 16-bit port size

11 32-bit port size

See Section 11.3.1, “Base Registers (BRx).”

6CIP1

Core initial prefix. Defines the initial value of MSR[IP]. Exception prefix. The setting of this bit

specifies whether an exception vector offset is prepended with Fs or 0s. In the following

description,

nnnnn is the offset of the exception vector.

0 MSR[IP] = 1 (default). Exceptions are vectored to the physical address 0xFFF

n_nnnn

1 MSR[IP] = 0 Exceptions are vectored to the physical address 0x000

n_nnnn.

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