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Reset

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

5-10

Freescale Semiconductor

5.4.2

Hard Reset Configuration Examples

This section presents some examples of hard reset configurations in different systems.

5.4.2.1

Single MPC8280 with Default Configuration

This is the simplest configuration scenario. It can be used if the default values achieved by clearing the

hard reset configuration word are desired. This is applicable only for systems using single-MPC8280 bus

mode (as opposed to 60x bus mode). To enter this mode, tie RSTCONF to VCC as shown in Figure 5-5.

The MPC8280 does not access the boot EPROM; it is assumed that the default configuration is used upon

exiting hard reset.

Figure 5-5. Single Chip with Default Configuration

5.4.2.2

Single MPC8280 Configured from Boot EPROM

For a configuration that differs from the default, the MPC8280 can be used as a configuration master by

tying RSTCONF to GND as shown in Figure 5-6. The MPC8280 can access the boot EPROM. It is

assumed the configuration is as defined there upon exiting hard reset.

ALD_EN

CP auto load enable. Allows the CP to automatically load the essential PCI configuration

registers from the EEPROM during reset.

0 CP auto load is disabled.

1 CP auto load is enabled.

—

Reserved, should be cleared.

28–31

MODCK_H

High-order bits of the MODCK bus, which determine the clock reset configuration. See

Chapter 10, “Clocks and Power Control,” for details.

Note: If the device is configured to PCI mode (PCI_MODE is driven low), this field has no effect

and the value for MODCK_H is loaded directly from the MODCK_H pins. Note that the

value of the MODCK_H bits are derived from the dedicated PCI_MODCK_H[0:3] pins

when operating in PCI mode.

1 The user should exercise caution when changing this bit. This bit has an immediate effect on the external bus and

may result in unstable system operation.

Table 5-7. Hard Reset Configuration Word Field Descriptions (continued)

Bits

Name

Description

Configuration

Slave Chip

PORESET

RSTCONF

D[0–31]

A[0–31]

HRESET

Vcc

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