MPC8280 datasheet(226/1386 Pages) FREESCALE

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Reset

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

5-2

Freescale Semiconductor

5.1.1

Reset Actions

The reset block has a reset control logic that determines the cause of reset, synchronizes it if necessary, and

resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller,

and parallel I/O pins are initialized only on hard reset. Soft reset initializes the internal logic while

maintaining the system configuration. Because there is no soft nor hard reset in the 603e core, asserting

external SRESET generates a reset to the 603e core and a soft reset to the remainder of the device, The

impact on the given application is the reset to the core resets the MSR[IP] to the value in the HRCW[CIP],

see Table 5-7.

Table 5-2 identifies reset actions for each reset source.

5.1.2

Power-On Reset Flow

Assertion of the PORESET external pin initiates the power-on reset flow. PORESET should be asserted

externally for at least 16 input clock cycles after external power to the chip reaches at least 2/3 Vcc. The

value driven on RSTCONF while PORESET changes from assertion to negation determines the chip

configuration. If RSTCONF is negated (driven high) while PORESET changes, the chip acts as a

configuration slave. If RSTCONF is asserted while PORESET changes, the chip acts as a configuration

master. Section 5.4, “Reset Configuration,” explains the configuration sequence and the terms

‘configuration master’ and ‘configuration slave.’

Directly after the negation of PORESET and choice of the reset operation mode as configuration master

or configuration slave, the MPC8280 starts the configuration process. The MPC8280 asserts HRESET and

SRESET throughout the power-on reset process, including configuration. Configuration takes 1,024

CLOCKIN cycles, after which MODCK[1–3] are sampled to determine the chips working mode. Next the

MPC8280 halts until the main PLL locks. As described in Section 10.6, “Clock Configuration Modes,” the

main PLL locks according to MODCK[1–3], which are sampled, and to MODCK_HI (MODCK[4–7])

taken from the reset configuration word. The main PLL lock can take up to 200 µs depending on the

specific chip. During this time HRESET and SRESET are asserted. When the main PLL is locked, the

clock block starts distributing clock signals in the chip. HRESET remains asserted for another 512 clocks

and is then released. The SRESET is released three clocks later.

Table 5-2. Reset Actions for Each Reset Source

Reset Source

Reset Logic

and PLL

States Reset

System

Configuration

Sampled

Clock

Module

Reset

HRESET

Driven

Other

Internal

Logic Reset1

1 Includes all other CPM and core logic not explicitly noted elsewhere in the table.

SRESET

Driven

Core

Reset

Power-on reset

Yes

External hard reset

Software watchdog

Bus monitor

Checkstop

Yes

JTAG reset

External soft reset

Yes

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