MPC8280 datasheet(233/1386 Pages) FREESCALE

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Reset

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

5-9

ISPS1

Internal space port size. Defines the initial value of BCR[ISPS]. Setting ISPS configures the

MPC8280 to respond to accesses from a 32-bit external master to its internal space. See

Section 4.3.2.1, “Bus Configuration Register (BCR).”

8–9

L2CPC1

L2 cache pins configuration. Defines the initial value of SIUMCR[L2CPC]. See Section 4.3.2.6,

“SIU Module Configuration Register (SIUMCR).”

10–11

DPPC1

Data parity pin configuration. Defines the initial value of SIUMCR[DPPC]. For more details refer

to Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR).”

PLLBP

PLL bypass

0 Normal operation

1 Bypass CPM PLL

13–15

ISB

Initial internal space base select. Defines the initial value of IMMR[0–14] and determines the

base address of the internal memory space.

000 0x0000_0000

001 0x00F0_0000

010 0x0F00_0000

011 0x0FF0_0000

100 0xF000_0000

101 0xF0F0_0000

110 0xFF00_0000

111 0xFFF0_0000

See Section 4.3.2.7, “Internal Memory Map Register (IMMR).”

BMS

Boot memory space. Defines the initial value for BR0[BA]. There are two possible boot memory

regions: HIMEM and LOMEM.

0 0xFE00_0000—0xFFFF_FFFF

1 0x0000_0000—0x01FF_FFFF

See Section 11.3.1, “Base Registers (BRx).”

BBD1

Bus busy disable. Defines the initial value of SIUMCR[BBD]. See Section 4.3.2.6, “SIU Module

Configuration Register (SIUMCR).”

18–19

MMR

Mask masters requests. Defines the initial value of SIUMCR[MMR]. See Section 4.3.2.6, “SIU

Module Configuration Register (SIUMCR).”

20–21

LBPC1

Local bus pin configuration. Defines the value of SIUMCR[LBPC]. See Section 4.3.2.6, “SIU

Module Configuration Register (SIUMCR).”

00 Local bus pins function as local bus

01 Local bus pins function as PCI bus

10 Local bus pins function as core pins

11 Reserved

22–23

APPC1

Address parity pin configuration. Defines the initial value of SIUMCR[APPC]. See

Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR).”

24–25

CS10PC1

CS10 pin configuration. Defines the initial value of SIUMCR[CS10PC]. See Section 4.3.2.6,

“SIU Module Configuration Register (SIUMCR).”

Note: During the reset configuration sequence, the BCTL1/CS10 pin toggles like POE of the 60x

bus GPCM, regardless of the configuration of the reset configuration word. After the reset

configuration sequence, the BCTL1/CS10 pin behaves according to the configuration of

SIUMCR[CS10PC].

Table 5-7. Hard Reset Configuration Word Field Descriptions (continued)

Bits

Name

Description

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