MPC8280 datasheet(228/1386 Pages) FREESCALE

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Reset

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

5-4

Freescale Semiconductor

5.2

Reset Status Register (RSR)

The reset status register (RSR), shown in Figure 5-2, is memory-mapped into the MPC8280’s SIU register

map.

Table 5-3 describes RSR fields.

Field

—

R/W

Reset

0000_0000_0000_0000

Addr

0x10C90

Field

—

JTRS CSRS

SWRS

BMRS ESRS EHRS

R/W

Reset

0000_0000_0000_0011

Addr

0x10C92

Figure 5-2. Reset Status Register (RSR)

Table 5-3. RSR Field Descriptions

Bits

Name

Function

0–25

—

Reserved, should be cleared.

JTRS

JTAG reset status. When the JTAG reset request is set, JTRS is set and remains set until software

clears it. JTRS is cleared by writing a 1 to it (writing zero has no effect).

0 No JTAG reset event occurred

1 A JTAG reset event occurred

CSRS

Check stop reset status. When the core enters a checkstop state and the checkstop reset is enabled

by the RMR[CSRE], CSRS is set and it remains set until software clears it. CSRS is cleared by

writing a 1 to it (writing zero has no effect).

0 No enabled checkstop reset event occurred

1 An enabled checkstop reset event occurred

SWRS Software watchdog reset status. When a software watchdog expire event (which causes a reset) is

detected, the SWRS bit is set and remains that way until the software clears it. SWRS is cleared by

writing a 1 to it (writing zero has no effect).

0 No software watchdog reset event occurred

1 A software watchdog reset event has occurred

BMRS Bus monitor reset status. When a bus monitor expire event (which causes a reset) is detected,

BMRS is set and remains set until the software clears it. BMRS can be cleared by writing a 1 to it

(writing zero has no effect).

0 No bus monitor reset event has occurred

1 A bus monitor reset event has occurred

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