MPC8280 datasheet(216/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

4-44

Freescale Semiconductor

Table 4-19 describes TMCNTSC fields.

4.3.2.15

Time Counter Register (TMCNT)

The time counter register (TMCNT), shown in Figure 4-36, contains the current value of the time counter.

The counter is reset to zero on PORESET reset or hard reset but is not effected by soft reset.

Field

—

SEC

ALR

—

SIE

ALE

TCF

TCE

Reset

0000_0000_0000_0000

R/W

Addr

0x10220

Figure 4-35. Time Counter Status and Control Register (TMCNTSC)

Table 4-19. TMCNTSC Field Descriptions

Bits

Name

Description

0–7

—

Reserved, should be cleared.

SEC

Once per second interrupt. This status bit is set every second and should be cleared by software.

ALR

Alarm interrupt. This status bit is set when the value of the TMCNT is equal to the value programmed

in the alarm register.

10–11

—

Reserved, should be cleared.

SIE

Second interrupt enable.

0 The time counter does not generate an interrupt when SEC is set.

1 The time counter generates an interrupt when SEC is set.

ALE

Alarm interrupt enable. If ALE = 1, the time counter generates an interrupt when ALR is set.

TCF

Time counter frequency. The input clock to the time counter may be either 4 MHz or 32 KHz. The

user should set the TCF bit according to the frequency of this clock.

0 The input clock to the time counter is 4 MHz.

1 The input clock to the time counter is 32 KHz.

See Section 4.1.2, “Timers Clock” for further details.

TCE

Time counter enable. Is not affected by soft or hard reset.

0 The time counter is disabled.

1 The time counter is enabled.

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