MPC8280 datasheet(218/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

4-46

Freescale Semiconductor

4.3.3

Periodic Interrupt Registers

The periodic interrupt registers are described in the following sections.

4.3.3.1

Periodic Interrupt Status and Control Register (PISCR)

The periodic interrupt status and control register (PISCR), shown in Figure 4-38, contains the interrupt

request level and the interrupt status bit. It also contains the controls for the 16 bits to be loaded in a

modulus counter.

Table 4-21 describes PISCR fields.

Field

—

PIE

PTF

PTE

Reset

0000_0000_0000_0000

R/W

Addr

0x10240

Figure 4-38. Periodic Interrupt Status and Control Register (PISCR)

Table 4-21. PISCR Field Descriptions

Bits

Name

Description

0–7

—

Reserved, should be cleared.

Periodic interrupt status. Asserted if the PIT issues an interrupt. The PIT issues an interrupt after the

modulus counter counts to zero. The PS bit can be negated by writing a one to PS. A write of zero has

no effect on this bit.

9–12

—

Reserved, should be cleared.

PIE

Periodic interrupt enable. If PIE = 1, the periodic interrupt timer generates an interrupt when PS = 1.

PTF

Periodic interrupt frequency. The input clock to the periodic interrupt timer may be either 4 MHz or

32 KHz. The user should set the PTF bit according to the frequency of this clock.

0 The input clock to the periodic interrupt timer is 4 MHz.

1 The input clock to the periodic interrupt timer is 32 KHz.

See Section 4.1.2, “Timers Clock,” for further details

PTE

Periodic timer enable. This bit controls the counting of the periodic interrupt timer. When the timer is

disabled, it maintains its old value. When the counter is enabled, it continues counting using the

previous value.

0 Disable counter.

1 Enable counter

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