MPC8280 datasheet(214/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

4-42

Freescale Semiconductor

4.3.2.12

Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)

The local bus transfer error status and control register 1 (L_TESCR1) is shown in Figure 4-33.

The L_TESCR1 register bits are described in Table 4-17.

Field

—

PAR

—

Reset

0000_0000_0000_0000

R/W

Addr

0x10048

Field

—

DMD

—

DER

—

Reset

0000_0000_0000_0000

R/W

Addr

0x1004A

Note: Bits 0–15 and 19–23 are status bits and are cleared by writing 1s.

Figure 4-33. Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)

Table 4-17. L_TESCR1 Field Descriptions

Bits

Name

Description

Bus monitor time-out. Indicates that TEA was asserted due to the local bus monitor time-out.

—

Reserved, should be cleared.

PAR

Parity error. Indicates that MCP was asserted due to parity error on the local bus. L_TESCR2[PB]

indicates the byte lane that caused the error and L_TESCR2[BNK] indicates which memory

controller bank was accessed.

3–4

—

Reserved, should be cleared.

Write protect error. Indicates that a write was attempted to a local bus memory region that was

defined as read-only in the memory controller. Note that this alone does not cause TEA assertion.

Usually, in this case, the bus monitor will time-out.

—

Reserved, should be cleared.

7–9

Transfer code. Indicates the transfer code of the local bus transaction that caused the TEA.

000 60x-local bridge

001 Reserved

010 Local DMA function code 0

011 Local DMA function code 1

1xx Reserved

—

Reserved, should be cleared.

11–15

Transfer type. Indicates the transfer type of the local bus transaction that caused the TEA.

Section 8.4.3.1, “Transfer Type Signal (TT[0–4]) Encoding,” describes the various transfer types.

—

Reserved, should be cleared.

DMD

Data errors disable. Setting this bit disables parity errors on the local bus.

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