MPC8280 datasheet(212/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

4-40

Freescale Semiconductor

—

Reserved, should be cleared.

11–15

Transfer type. These bits indicates the transfer type of the 60x bus transaction that caused the TEA or

MCP. See Section 8.4.3.1, “Transfer Type Signal (TT[0–4]) Encoding,” for a description of the various

transfer types.

—

Reserved, should be cleared.

DMD

Data errors disable.

0 Errors are enabled.

1 All data errors (parity and single and double ECC errors) on the 60x bus are disabled.

—

Reserved, should be cleared.

PCIMCP PCI machine check. Set when a core machine check is asserted from the PCI bridge.

DER

.Data error. Set when a core machine check is asserted due to ECC or parity errors.

IRQ0

External machine check. Set when a machine check is asserted due to the external machine check pin

(IRQ0).

SWD

Software watchdog time-out. Indicates that a core machine check was asserted due to a time-out in the

software watchdog. See Section 4.1.5, “Software Watchdog Timer.”

ADO

60x bus monitor address-only time-out. Set when a core machine check is asserted due to time-out of the

bus monitor in an address only transaction. See Section 4.1.1, “Bus Monitor.”

24–31

ECNT

Single ECC error counter. Indicates the number of single ECC errors that occurred in the system. When

the counter reaches its maximum value (255), MCP is asserted for all single ECC errors. This feature

gives the system the ability to withstand a few random errors yet react to a catastrophic failure. The user

can set a lower threshold to the number of tolerated single ECC errors by writing some value to ECNT.

The counter starts from this value instead of zero.

Table 4-15. TESCR1 Field Descriptions (continued)

Bits

Name

Description

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