MPC8280 datasheet(213/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

4-41

4.3.2.11

60x Bus Transfer Error Status and Control Register 2 (TESCR2)

The 60x bus transfer error status and control register 2 (TESCR2) is shown in Figure 4-32.

The TESCR2 register is described in Table 4-16.

Field

—

REGS DPR

—

PCI0

PCI1

—LCL

Reset

0000_0000_0000_0000

R/W

Addr

0x10044

Field

BNK

—

Reset

0000_0000_0000_0000

R/W

Addr

0x10046

Note: all bits are status bits and are cleared by writing 1s.

Figure 4-32. 60x Bus Transfer Error Status and Control Register 2 (TESCR2)

Table 4-16. TESCR2 Field Descriptions

Bits

Name

Description

—

Reserved, should be cleared.

REGS

Internal registers error. An error occurred in a transaction to the MPC8280’s internal registers.

DPR

Dual port ram error. An error occurred in a transaction to the MPC8280’s dual-port RAM.

—

Reserved, should be cleared.

PCI0

PCI memory space 0 error. An error occurred in a transaction to the PCI memory space configured

by PCIBR0 and PCIMSK0.

PCI1

PCI memory space 1 error. An error occurred in a transaction to the PCI memory space configured

by PCIBR1 and PCIMSK1.

—

Reserved, should be cleared.

LCL

Local bus bridge error. An error occurred in a transaction to the MPC8280’s 60x bus to local bus

bridge.

8–15

Parity error on byte. There are eight parity error status bits, one per 8-bit lane. A bit is set for the

byte that had a parity error.

16–27

BNK

Memory controller bank. There are twelve error status bits, one per memory controller bank. A bit

is set for the 60x bus memory controller bank that had an error. Note that this field is invalid if the

error was not caused by ECC or parity checks.

28–31

—

Reserved, should be cleared.

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