MPC8280 datasheet(215/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

4-43

4.3.2.13

Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)

The local bus transfer error status and control register 2 (L_TESCR2) is shown in Figure 4-34.

Table 4-18 describes L_TESCR2 fields.

4.3.2.14

Time Counter Status and Control Register (TMCNTSC)

The time counter status and control register (TMCNTSC), shown in Figure 4-35, is used to enable the

different TMCNT functions and for reporting the source of the interrupts. The register can be read at any

time. Status bits are cleared by writing ones; writing zeros does not affect the value of a status bit.

18–19

—

Reserved, should be cleared.

DER

Data error. Set when a core machine check is asserted due to parity errors in the local bus.

21–31

—

Reserved, should be cleared.

Field

—

Reset

0000_0000_0000_0000

R/W

Addr

0x1004C

Field

BNK

—

Reset

0000_0000_0000_0000

R/W

Addr

0x1004E

Note: all bits are status bits and are cleared by writing 1s.

Figure 4-34. Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)

Table 4-18. L_TESCR2 Field Descriptions

Bits

Name

Description

0–11

—

Reserved, should be cleared.

12–15

Parity error on byte. There are four parity error status bits, one per 8-bit lane. A bit is set for the byte

that had a parity error.

16–27

BNK

Memory controller bank. There are twelve error status bits, one per memory controller bank. A bit is

set for the local bus memory controller bank that had an error. Note that BNK is invalid if the error

was not caused by ECC or PARITY checks.

28–31

—

Reserved, should be cleared.

Table 4-17. L_TESCR1 Field Descriptions (continued)

Bits

Name

Description

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