MPC8280 datasheet(211/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

4-39

4.3.2.10

60x Bus Transfer Error Status and Control Register 1 (TESCR1)

The 60x bus transfer error status and control register 1 (TESCR1) is shown in Figure 4-31.

Table 4-15 describes TESCR1 fields.

Field

ISBE PAR

ECC2

ECC1

EXT

—

Reset

0000_0000_0000_0000

R/W

Addr

0x10040

Field

—

DMD

—

PCIMCP

DER IRQ0 SWD ADO

ECNT

Reset

0000_0000_0000_0000

R/W

Addr

0x10042

Note: Bits 0–15 and 19–23 are status bits and are cleared by writing 1s.

Figure 4-31. 60x Bus Transfer Error Status and Control Register 1 (TESCR1)

Table 4-15. TESCR1 Field Descriptions

Bits

Name

Description

60x bus monitor time-out. Set when TEA is asserted due to the 60x bus monitor time-out.

ISBE

Internal space bus error. Indicates that one of the following occurred:

•TEA was asserted due to an error on a transaction to MPC8280’s internal memory space

• An MCP was caused by a parity error on a transaction to MPC8280’s internal memory space. Possible

only if BCR[SPAR] = 1.

TESCR2[REGS,DPR, LCL, PCI0, PCI1] indicate which of MPC8280’s internal slaves caused the error.

PAR

60x bus parity error. Indicates that an MCP was caused due to one of the following:

• Parity error on 60x bus access controlled by the memory controller. TESCR2[PB] indicates which byte

lane caused the error; TESCR2[BNK] indicates which memory controller bank was accessed.

• Parity error on a transaction to MPC8280’s internal memory space. Possible only if BCR[SPAR] = 1.

ECC2

Double ECC error. Indicates that MCP was asserted due to double ECC error on the 60x bus.

TESCR2[BNK] indicates which memory controller bank was accessed.

ECC1

Single ECC error. Indicates that MCP was asserted due to single bit ECC error on the 60x bus.

TESCR2[BNK] indicates which memory controller bank was accessed. Single-bit errors are fixed by the

ECC logic. However, if the ECC counter (ECNT) has reached its maximum value, all single-bit errors

cause the assertion of MCP.

Write protect error. Indicates that a write was attempted to a 60x bus memory region that was defined as

read-only in the memory controller. Note that this alone does not cause TEA assertion. Usually, in this

case, the bus monitor will time-out.

EXT

External error. Indicates that TEA was asserted by an external bus slave.

7–9

Transfer code. Indicates the transfer code of the 60x bus transaction that caused the TEA or MCP. See

Section 8.4.3.2, “Transfer Code Signals TC[0–2],” for a description of the various transfer codes.

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