MPC8280 datasheet(208/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

4-36

Freescale Semiconductor

4.3.2.7

Internal Memory Map Register (IMMR)

The internal memory map register (IMMR), shown in Figure 4-29, contains identification of a specific

device as well as the base address for the internal memory map. Software can deduce availability and

location of any on-chip system resources from the values in IMMR. PARTNUM and MASKNUM are

mask programmed and cannot be changed for any particular device.

LPBSE

Local bus parity byte select enable.

0 Parity byte select is disabled. LGPL4 output of UPM is available for memory control.

1 Parity byte select is enabled. LGPL4 pin is used as local bus parity byte select output from the

MPC8280.

—

Reserved, should be cleared.

DBA

Data output buffer impedance configuration. The pins in this group include D[0-63] and

PWE[0-7]/PSDDQM[0-7]/PBS[0-7].

0 The output buffer typical impedance is 45

Ω.

1 The output buffer typical impedance is 25

Ω.

ABA

Address output buffer impedance configuration. The pins in this group include A[0-31],

PSDA10/PGPL0, PSDWE/PGPL1, POE/PSDRAS/PGPL2, PSDCAS/PGPL3, PGTA/PUPM,

WAIT/PGPl4, PSDAMUX/PGPL5 and BNKSEL[0:2].

0 The output buffer typical impedance is 45

Ω.

1 The output buffer typical impedance is 25

Ω.

22–31

—

Reserved, should be cleared.

Field

ISB

—

Reset

Depends on reset configuration sequence. See Section 5.4.1, “Hard Reset Configuration Word.”

R/W

Addr

0x101A8

Field

PARTNUM

MASKNUM

Reset

0000_1010

0000_0000

R/W

Addr

0x101AA

Figure 4-29. Internal Memory Map Register (IMMR)

Table 4-12. SIUMCR Register Field Descriptions (continued)

Bits

Name

Description

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