MPC8280 datasheet(207/1386 Pages) FREESCALE

207 / 1386 page

System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

4-35

8–9

LBPC

Local bus pins configuration.

Note: LBPC should be programmed only during the hard reset configuration sequence (using the hard

reset configuration word).

00 Local bus pins function as local bus

01 Local bus pins function as PCI bus. Reserved on all other devices.

10 Local bus pins function as core pins

11 Reserved

10–11

APPC

Address parity pins configuration. Note that during power on reset the MODCK pins are used for PLL

configuration. The pin multiplexing indicated in the table applies only to normal operation. Selection

between IRQ7 and INT_OUT is according to CPU state. If the core is disabled, the pin is INT_OUT;

otherwise it is IRQ7.

APPC

MODCK1/AP(1)/TC(0)/

BNKSEL(0)

TC(0)

AP(1)

BNKSEL(0)

—

MODCK2/AP(2)/TC(1)/

BNKSEL(1)

TC(1)

AP(2)

BNKSEL(1)

MODCK3/AP(3)/TC(2)/

BNKSEL(2)

TC(2)

AP(3)

BNKSEL(2)

IRQ7/INT_OUT/APE

IRQ7/

INT_OUT

APE

IRQ7/

INT_OUT

IRQ7/

INT_OUT

CS11/AP(0)

CS11

AP(0)

CS11

—

12–13

CS10PC Chip select 10-pin configuration.

CS10PC

CS10/BCTL1

CS10

BCTL1

—

14–15

BCTLC

Configuration for the control lines for external buffers.

00 BCTL0 is used as W/R control for external buffers. BCTL1 is used as OE control for external buffers.

01 BCTL0 is used as W/R control for external buffers. BCTL1 is used as OE control for external buffers.

10 BCTL0 is used as WE control for external buffers. BCTL1 is used as RE control for external buffers.

11 Reserved

16-17

MMR

Mask masters requests. In some systems, several bus masters are active during normal operation; only

one should be active during boot sequence. The active master, which is the boot device, initializes

system memories and devices and enables all other masters. MMR facilitates such a boot scheme by

masking the selected master’s bus requests. MMR can be configured through the hard reset

configuration sequence (see Section 5.4.2, “Hard Reset Configuration Examples”). Typically system

configuration identifies only one master is the boot device, which initializes the system and then

enables all other devices by writing 00 to MMR.

Note: It is not recommended to mask the request of a master which is defined as the parked master in

the arbiter, since this cannot prevent this master from getting a bus grant.

00 No masking on bus request lines.

01 Reserved

10 The MPC8280’s internal core bus request masked and external bus requests two and three masked

(boot master connected to external bus request 1).

11 All external bus requests masked (boot master is the MPC8280’s internal core).

Table 4-12. SIUMCR Register Field Descriptions (continued)

Bits

Name

Description

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