PM7366-PI datasheet(112/286 Pages) PMC

112 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

is set low, Big Endian format is selected. When LENDIAN is set high, Little Endian format is

selected. Descriptor references and the contents of descriptors are always transferred in

Little Endian Format. Please refer below for each format's byte ordering.

Table 16 – Big Endian Format

Bit 31

Bit 0

DWORD Address

BYTE 0

BYTE 1

BYTE 2

BYTE 3

BYTE 4

BYTE 5

BYTE 6

BYTE 7

•

n-4

BYTE n-4

BYTE n-3

BYTE n-2

BYTE n-1

Table 17 – Little Endian Format

Bit 31

Bit 0

DWORD Address

BYTE 3

BYTE 2

BYTE 1

BYTE 0

BYTE 7

BYTE 6

BYTE 5

BYTE 4

•

n-4

BYTE n-1

BYTE n-2

BYTE n-3

BYTE n-4

SOE_E:

The stop on error enable (SOE_E) bit determines the action the PCI controller will take when

a system or parity error occurs. When set high the PCI controller will disconnect the PCI

REQB signal from the PCI bus. This prevents the GPIC from the becoming a master device

on the PCI bus in event of one of the following bits in the PCI Configuration Command/Status

controller will continue to allow master transactions on the PCI bus. Setting this bit low after

an error has occurred or clearing the appropriate bit the PCI Configuration Command/Status

masters. In the event of a system or parity error it is recommended that the core device be

reset unless the cause of the fault can be determined.

PONS_E:

The Report PERR on SERR enable (PONS_E) bit controls the source of system errors.

When set high all parity errors will be signaled to the host via the SERRB output signal.

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