LPC55S2X datasheet(96/132 Pages) NXP

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NXP Semiconductors

LPC55S2x/LPC552x

32-bit Arm Cortex®-M33 microcontroller

Tamb = -40 °C to +105 °C; VDDA = 1.8 V to 3.6 V; ADC calibrated at T = 25 °C.

Symbol

Parameter

Conditions

Min[1]

Typ[1]

Max[1]

Unit

16-bit differential mode,

CTYPE = 2

[3][1][4][5][6] -0.99

2.6

LSB

differential

linearity error

16-bit single ended mode,

CTYPE = 1

[3][1][4][5][6] -1

+9.5

LSB

16-bit differential mode,

CTYPE = 2

[3][1][4][5][7] -16

+16

LSB

EL(adj)

integral non-

linearity

16-bit single ended mode,

CTYPE = 1

[3][1][4][5][7] -12

+12

LSB

offset error

uncalibrated

[3][8] -

2.3

Verr(FS)

full-scale error

voltage

uncalibrated

[3][9] -

LSB

16-bit differential mode,

CTYPE = 2

[10] -

12.6

bits

ENOB

[L:] Effective

number of bits

16-bit single ended mode,

CTYPE = 1

[10] -

12.0

bits

16-bit differential mode,

CTYPE = 2

[10] -

-85

THD

[L:] Total

Harmonic

Distortion

16-bit single ended mode,

CTYPE = 1

[10] -

-85

16-bit differential mode,

CTYPE = 2

[10] -

SFDR

[L:] Spurious Free

Dynamic Range

16-bit single ended mode,

CTYPE = 1

[10] -

tADCSTUP Analog startup

time

Wait time after setting

ADC_CTRL[ADCEN] [10]

[11] -

Table 41. 16-bit ADC static characteristics...continued

[1]

The values listed are typical values and are not guaranteed. Based on characterization. Not tested in production. If VREFP is less than VDDA, then

voltage inputs greater than VREFP and less than VDDA are allowed but result in a full scale conversion result.

[2]

To use temperature sensor, the maximum fclk(ADC) frequency is 6 MHz.

[3]

Linear data collected using a linear histogram technique.

[4]

fclk(ADC) = 24 MHz, STS = 3, Power select = 1, Average setting = 1, fs = 1 Msample/s

[5]

Differential linear results assume offset 0.2% from VREFL and 0.2% from VREFH

[6]

The differential linearity error (ED) is the difference between the actual step width and the ideal step width.

[7]

The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate

adjustment of gain and offset errors.

[8]

The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. For best

performance, force the offset calibration to -16. Set this prior to performing the gain calibration.

[9]

The full-scale error voltage or gain error (EG) is the difference between the straight-line fitting the actual transfer curve after removing offset error, and the

straight line which fits the ideal transfer curve.

[10] Input data is 1kHz sine wave, ADC conversion clock 24 MHz, Power Select = 3, Average setting = 4.

[11] Value of ADC_CFG[PUDLY] * 4 * ADCclk must be > tADCSTUP.

12.2.1 ADC input resistance (Please refer to the ADC Inputs Selection & ADC programming

table in the UM)

Tamb = -40 °C to +105 °C

Min

Typ

Max

Unit

Input resistance

Table 42. ADC input resistance

LPC55S2X_LPC552X

All information provided in this document is subject to legal disclaimers.

Data sheet

Rev. 2.3 — 29 August 2024

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