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LPC55S2X датащи(PDF) 1 Page - NXP Semiconductors |
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LPC55S2X датащи(HTML) 1 Page - NXP Semiconductors |
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1 / 132 page ![]() LPC55S2x/LPC552x 32-bit Arm Cortex®-M33 microcontroller Rev. 2.3 — 29 August 2024 Data sheet 1 General description The LPC55S2x/LPC552x is an ARM Cortex-M33 based microcontroller for embedded applications. These devices include a CASPER Crypto/FFT engine, up to 256 KB of on-chip SRAM, up to 512 KB on-chip flash, PRINCE module for on-the-fly flash encryption/decryption, high-speed and full-speed USB host and device interface with crystal-less operation for full-speed, SD/MMC/SDIO interface, five general-purpose timers, one SCTimer/PWM, one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), nine flexible serial communication peripherals (which can be configured as a USART, SPI, high speed SPI, I2C, or I2S interface), Programmable Logic Unit (PLU), one 16-bit 1.0 Msamples/sec ADC capable of simultaneous conversions, comparator, and temperature sensor. To support security requirements, the LPC55S2x also offers support for secure boot, HASH, AES, RSA, UUID, dynamic encrypt and decrypt, debug authentication, and TBSA compliance. 2 Features and benefits • ARM Cortex-M33 core (r0p3): – Running at a frequency of up to 150 MHz. – Memory Protection Unit (MPU). – ARM Cortex M33 built-in Nested Vectored Interrupt Controller (NVIC). – Non-maskable Interrupt (NMI) input with a selection of sources. – Serial Wire Debug with eight breakpoints and four watch points. Includes Serial Wire Output for enhanced debug capabilities. – System tick timer. – The configuration of this instance includes MPU, FPU, DSP, and ETM. • CASPER Crypto co-processor is provided to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms, such as, Elliptic Curve Cryptography (ECC). • On-chip memory: – Up to 512 KB on-chip flash program memory with flash accelerator and 512 byte page erase and write. – Up to 256 KB total SRAM consisting of 32 KB SRAM on Code Bus, 208 KB SRAM on System Bus (192 KB is contiguous), and additional 16 KB USB SRAM on System Bus which can be used by the USB interface or for general purpose use. • PRINCE module for real-time encryption of data being written to on-chip flash and decryption of encrypted flash data during read to allow asset protection, such as securing application code, and enabling secure flash update. • On-chip ROM bootloader supports: – Booting of images from on-chip flash – Supports CRC32 image integrity checking. – Supports flash programming through In System Programming (ISP) commands over following interfaces: USB0/1 interfaces using HID Class device, UART interface (Flexcomm 0) with auto baud, SPI slave interfaces (Flexcomm 3 or 9) using mode 3 (CPOL = 1 and CPHA = 1), and I2C slave interface (Flexcomm 1) |
Аналогичный номер детали - LPC55S2X |
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Аналогичное описание - LPC55S2X |
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