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LPC55S2X датащи(PDF) 9 Page - NXP Semiconductors

номер детали LPC55S2X
подробное описание детали  32-bit Arm Cortex®-M33 microcontroller
PDF  132 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC55S2X датащи(HTML) 9 Page - NXP Semiconductors

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NXP Semiconductors
LPC55S2x/LPC552x
32-bit Arm Cortex®-M33 microcontroller
Symbol
59 pin
VFBGA
64 pin
HTQFP
98 pin
VFBGA
100 pin
HLQFP
Reset
state
[1]
Type Function
#
Description
8
R
Reserved.
9
R
Reserved.
I/O 10
SEC_PIO0_0
Secure GPIO pin.
I/O 0
PIO0_1
General-purpose digital input/output pin.
1
R
Reserved.
I/O 2
FC3_CTS_SDA_SSEL0
Flexcomm 3: USART clear-to-send, I2C data
I/O, SPI Slave Select 0.
I
3
CTIMER_INP0
Capture input to CTIMER input muxes.
I
4
SCT0_GPI1
Pin input 1 to SCTimer/PWM.
5
R
Reserved.
O
6
SD1_CLK
SD/MMC 1 card clock.
O
7
CMP0_OUT
Analog comparator 0 output.
8
R
Reserved.
9
R
Reserved.
PIO0_1
A1
2
F5
7
[3]
Z
I/O 10
SEC_PIO0_1
Secure GPIO pin.
I/O 0
PIO0_2
General-purpose digital input/output pin. In
boundary scan mode: TRST (Test Reset).
Remark: In ISP mode, this pin is set to the
Flexcomm 3 SPI MISO function.
I/O 1
FC3_TXD_SCL_MISO_WS
Flexcomm 3: USART transmitter, I2C clock,
SPI master-in/slave-out data I/O, I2S word-
select/frame.
I
2
CTIMER_INP1
Capture input to CTIMER input multiplexers.
PIO0_2/
TRST
B7
52
B11
81
[3][4] PD
O
3
SCT0_OUT0
Table 3. Pin description...continued
LPC55S2X_LPC552X
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Data sheet
Rev. 2.3 — 29 August 2024
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