LPC55S2X datasheet(49/132 Pages) NXP

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NXP Semiconductors

LPC55S2x/LPC552x

32-bit Arm Cortex®-M33 microcontroller

AHB

port

Start address

End address

Function [1]

0x0000 0000

0x0007 FFFF

Flash memory, on CM33 code bus.

0x0300 0000

0x0301 FFFF

Boot ROM, on CM33 code bus.

0x0400 0000

0x0400 7FFF

SRAM X on CM33 code bus, 32 KB. SRAMX_0 (0x1400 0000 to

0x1400 0FFF) and SRAMX_1 (0x1400 4000 to 0x1400 4FFF) are used

for Casper (total 8 KB). If CPU retention used in power-down mode,

SRAMX_2 (0x1400 6000 to 0x1400 65FF) is used (total 1.5 KB) by

default in power API and this is user configurable within SRAMX_2 and

SRAMX_3.

0x2000 0000

0x2000 FFFF

SRAM 0 on CM33 data bus, 64 KB.

0x2001 0000

0x2001 FFFF

SRAM 1 on CM33 data bus, 64 KB.

0x2002 0000

0x2002 FFFF

SRAM 2 on CM33 data bus, 64 KB.

0x2003 0000

0x2003 FFFF

Reserved

0x2004 0000

0x2004 3FFF

SRAM 4 on CM33 data bus, 16 KB.

0x4000 0000

0x4001 FFFF

AHB to APB bridge 0. See Section 7.16.

0x4002 0000

0x4003 FFFF

AHB to APB bridge 1. See Section 7.16.

0x4008 0000

0x4008 FFFF

AHB peripherals. See Section 7.17.

0x4009 0000

0x4009 FFFF

AHB peripherals. See Section 7.17.

0x400A 0000

0x400A FFFF

AHB peripherals. See Section 7.17.

0x4010 0000

0x4010 FFFF

AHB peripherals. See Section 7.17.

Table 5. Memory map overview

[1]

Gaps between AHB matrix slave ports are not shown.

7.16 APB peripherals

Table 6 provides details of the addresses for APB peripherals. APB peripherals have both secure and non-

secure access possibilities.

APB

bridge

Non-secure

base address

Secure

base address

Peripheral

0x4000 0000 0x5000 0000 Syscon.

0x4000 1000 0x5000 1000 IOCON. Pin function selection and pin control setup.

0x4000 2000 0x5000 2000 Group GPIO input interrupt 0 (GINT0)

0x4000 3000 0x5000 3000 Group GPIO input interrupt 1 (GINT1)

0x4000 4000 0x5000 4000 Pin interrupt and pattern match (PINT)

0x4000 5000 0x5000 5000 Secure pin interrupt and pattern match.

0x4000 6000 0x5000 6000 Input multiplexing 0 and frequency measure.

0x4000 7000 0x5000 7000 Reserved.

0x4000 8000 0x5000 8000 CT32B0 (standard counter/timer 0).

0x4000 9000 0x5000 9000 CT32B1 (standard counter/timer 1).

0x4000 C000 0x5000 C000 WWDT0 (windowed watchdog timer 0).

Table 6. APB peripherals memory map

LPC55S2X_LPC552X

All information provided in this document is subject to legal disclaimers.

Data sheet

Rev. 2.3 — 29 August 2024

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