LPC55S2X datasheet(64/132 Pages) NXP

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NXP Semiconductors

LPC55S2x/LPC552x

32-bit Arm Cortex®-M33 microcontroller

7.25.4 RTC timer

The RTC block to count seconds and generate an alarm interrupt to the processor whenever the counter value

equals the value programmed into the associated 32-bit match register.

7.25.4.1 Features

• The RTC oscillator has the following clock outputs: 32.768 kHz clock (named as 32 kHz clock in rest of this

chapter) 32 kHz clock, selectable for system clock and CLKOUT pin, 1 Hz clock for RTC timing, and 1024 Hz

clock (named as 1 kHz clock in rest of this chapter) for high-resolution RTC timing.

• 32-bit, 1 Hz RTC counter and associated match register for alarm generation.

• 15-bit, 32KHz sub-second counter.

• Separate 16-bit high-resolution/wake-up timer clocked at 1 kHz for 1 ms resolution with a more that one

minute maximum time-out period.

• RTC alarm and high-resolution/wake-up timer time-out each generate independent interrupt requests that go

to one NVIC channel. Either time-out can wake up the part from any of the low power modes, including deep

power-down.

• Eight 32-bit general purpose registers can retain data in deep power-down. These registers are reset only on

software reset of the RTC.

7.25.5 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each channel can be

programmed with an independent time interval, and each channel operates independently from the other

channels.

7.25.5.1 Features

• 24-bit interrupt timer.

• Four channels independently counting down from individually set values.

• Repeat interrupt, one-shot interrupt, and one-shot bus stall modes.

7.25.6 OS Timer

42-bit free running timer with individual match/capture and interrupt generation logic used as continuous time-

base for the system, available in any reduced power modes. It runs on 32kHz clock source, allowing a count

period of more than 4 years.

7.25.6.1 Features

• Central 42-bit, free-running gray-code event/timestamp timer.

Match registers compared to the main counter to generate an interrupt and/or wake-up event.

• Capture registers triggered by CPU command, readable via the AHB/IPS bus.

• APB interface for register access.

• IRQ and wake-up.

• Reads of gray-encoded timers are accomplished with no synchronization latency.

7.25.7 Micro-tick timer (UTICK)

The ultra-low power Micro-tick Timer, running from the Watchdog oscillator, can be used to wake up the device

from sleep and deep-sleep modes.

LPC55S2X_LPC552X

All information provided in this document is subject to legal disclaimers.

Data sheet

Rev. 2.3 — 29 August 2024

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