LPC55S2X datasheet(57/132 Pages) NXP

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NXP Semiconductors

LPC55S2x/LPC552x

32-bit Arm Cortex®-M33 microcontroller

– Level-sensitive interrupt pins can be HIGH-active or LOW-active.

– Pin interrupts can wake up the device from sleep mode, and deep-sleep mode.

• Pattern match engine:

– Up to eight pins can be selected from all digital pins on ports 0 and 1 to contribute to a boolean expression.

The boolean expression consists of specified levels and/or transitions on various combinations of these

pins.

– Each bit slice minterm (product term) comprising of the specified boolean expression can generate its own,

dedicated interrupt request.

– Any occurrence of a pattern match can also be programmed to generate an RXEV notification to the CPU.

The RXEV signal can be connected to a pin.

– Pattern match can be used in conjunction with software to create complex state machines based on pin

inputs.

– Pattern match engine facilities wake-up only from active and sleep modes.

7.23 Communication peripherals

7.23.1 Full-speed USB Host/Device Interface (USB0)

The USB is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals.

The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The

bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host

controller.

7.23.1.1 USB0 device controller

The device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of a register

interface, serial interface engine, endpoint buffer memory. The serial interface engine decodes the USB data

stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error

condition is indicated via status registers. An interrupt is also generated if enabled.

Features

• USB2.0 full-speed device controller supporting crystal-less operation in device mode using software library

example in technical note (TN00063).

• Supports ten physical (five logical) endpoints including one control endpoint.

• Single and double-buffering supported.

• Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.

• Supports wake-up from Deep-sleep mode on USB activity and remote wake-up.

• Supports SoftConnect.

• Link Power Management (LPM) supported.

7.23.1.2 USB0 host controller

The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists

of register interface, serial interface engine and DMA controller. The register interface complies with the Open

Host Controller Interface (OHCI) specification.

Features

• OHCI compliant.

• Two downstream ports.

LPC55S2X_LPC552X

All information provided in this document is subject to legal disclaimers.

Data sheet

Rev. 2.3 — 29 August 2024

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