LPC55S2X datasheet(2/132 Pages) NXP

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NXP Semiconductors

LPC55S2x/LPC552x

32-bit Arm Cortex®-M33 microcontroller

– ROM API functions: Flash programming API, Power control API, and Secure firmware update API using

NXP Secure Boot file format, version 2.0 (SB2 files).

– Supports booting of images from PRINCE encrypted flash regions.

– Support NXP Debug Authentication Protocol version 1.0 (RSA-2048) and 1.1 (RSA-4096).

– Supports setting a sealed part to Fault Analysis mode through Debug authentication.

• Secure Boot support:

– Uses RSASSA-PKCS1-v1_5 signature of SHA256 digest as cryptographic signature verification.

– Supports RSA-2048 bit public keys (2048 bit modulus, 32-bit exponent).

– Supports RSA-4096 bit public keys (4096 bit modulus, 32-bit exponent).

– Uses x509 certificate format to validate image public keys.

– Supports up to four revocable Root of Trust (RoT) or Certificate Authority keys, Root of Trust establishment

by storing the SHA-256 hash digest of the hashes of four RoT public keys in protected flash region (PFR).

– Supports anti-rollback feature using image key revocation and supports up to 16 Image key certificates

revocations using Serial Number field in x509 certificate.

• Serial interfaces:

– Flexcomm Interface contains up to nine serial peripherals (Flexcomm Interface 0-7 and Flexcomm Interface

8). Each Flexcomm Interface (except flexcomm 8, which is dedicated for high-speed SPI) can be selected

by software to be a USART, SPI, I2C, and I2S interface. Each Flexcomm Interface includes a FIFO that

supports USART, SPI, and I2S. A variety of clocking options are available to each Flexcomm Interface,

including a shared fractional baud-rate generator, and time-out feature.Flexcomm interfaces 0 to 7 each

provide one channel pair of I2S.

– I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to 1Mbit/s and with multiple

address recognition and monitor mode. Two sets of true I2C pads also support high-speed Mode (3.4 Mbit/s)

as a slave.

– USB 2.0 full speed host/device controller with on-chip PHY and dedicated DMA controller supporting crystal-

less operation in device mode using software library example in technical note (TN00063).

– USB 2.0 high-speed host/device controller with on-chip high-speed PHY.

• Digital peripherals:

– DMA0 controller with 23 channels and up to 22 programmable triggers, able to access all memories and

DMA-capable peripherals.

– DMA1 controller with 10 channels and up to 15 programmable triggers, able to access all memories and

DMA-capable peripherals.

– Secured digital input/output (SD/MMC and SDIO) card interface with DMA support. SDIO with support for up

to two cards. Supported card types are MMC, SDIO, and CE-ATA. Supports SD2.0, and SDR25 (52MHz).

– CRC engine block can calculate a CRC on supplied data using one of three standard polynomials with DMA

support.

– Up to 64 General-Purpose Input/Output (GPIO) pins.

– GPIO registers are located on the AHB for fast access. The DMA supports GPIO ports.

– Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising,

falling or both input edges.

– Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical

(AND/OR) combination of input states.

– I/O pin configuration with support for up to 16 function options.

– Programmable Logic Unit (PLU) to create small combinatorial and/or sequential logic networks including

state machines.

• Security Features:

– AES-256 encryption/decryption engine with keys fed directly from PUF or a software supplied key

– Secure Hash Algorithm (SHA2) module supports secure boot with dedicated DMA controller.

LPC55S2X_LPC552X

All information provided in this document is subject to legal disclaimers.

Data sheet

Rev. 2.3 — 29 August 2024

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