DSP56366P datasheet(100/110 Pages) FREESCALE

100 / 110 page

DSP56366 Technical Data, Rev. 3.1

5-4

Freescale Semiconductor

where:

ItypF2 = current at F2

ItypF1 = current at F1

= high frequency (any specified operating frequency)

= low frequency (any specified operating frequency lower than F2)

NOTE

F1 should be significantly less than F2. For example, F2 could be 66 MHz

and F1 could be 33 MHz. The degree of difference between F1 and F2

determines the amount of precision with which the current rating can be

determined for an application.

5.4

PLL Performance Issues

The following explanations should be considered as general observations on expected PLL behavior.

There is no testing that verifies these exact numbers. These observations were measured on a limited

number of parts and were not verified over the entire temperature and voltage ranges.

5.4.1

Phase Jitter Performance

The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL

and the internal DSP clock for a given device in specific temperature, voltage, input frequency and MF.

These variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz

and MF

≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10

and input frequencies greater than 10 MHz, this jitter is less than

±2 ns.

5.4.2

Frequency Jitter Performance

The frequency jitter of the PLL is defined as the variation of the frequency of the internal DSP clock. For

small MF (MF < 10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) this jitter is

between 0.5% and approximately 2%. For large MF (MF > 500), the frequency jitter is 2–3%.

5.4.3

Input (EXTAL) Jitter Requirements

The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL

is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency

of the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be

2%. The phase and frequency jitter performance results are only valid if the input jitter is less than the

prescribed values.

IMIPS

⁄

IMHz

⁄

(

typF2

ItypF1 ) F2 F1

()

⁄

–

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