DSP56366P datasheet(54/110 Pages) FREESCALE

54 / 110 page

DSP56366 Technical Data, Rev. 3.1

3-28

Freescale Semiconductor

169 CAS deassertion to RAS assertion

tCRP

4.25

× T

C − 4.0

59.8

—

49.1

—

170 CAS deassertion pulse width

tCP

2.75

× T

C − 4.0

37.7

—

30.4

—

171 Row address valid to RAS assertion

tASR

3.25

× T

C − 4.0

45.2

—

36.6

—

172 RAS assertion to row address not valid

tRAH

1.75

× T

C − 4.0

22.5

—

17.9

—

173 Column address valid to CAS assertion

tASC

0.75

× T

C − 4.0

7.4

—

5.4

—

174 CAS assertion to column address not valid

tCAH

3.25

× T

C − 4.0

45.2

—

36.6

—

175 RAS assertion to column address not valid

tAR

5.75

× T

C − 4.0

83.1

—

67.9

—

176 Column address valid to RAS deassertion

tRAL

× T

C − 4.0

56.6

—

46.0

—

177 WR deassertion to CAS assertion

tRCS

× T

C − 3.8

26.5

—

21.2

—

178 CAS deassertion to WR5 assertion

tRCH

1.25

× T

C − 3.7

15.2

—

11.9

—

179 RAS deassertion to WR5 assertion

tRRH

0.25

× T

C − 3.7

0.25

× T

C − 3.0

0.1

—

0.1

—

180 CAS assertion to WR deassertion

tWCH

× T

C − 4.2

41.3

—

33.3

—

181 RAS assertion to WR deassertion

tWCR

5.5

× T

C − 4.2

79.1

—

64.6

—

182 WR assertion pulse width

tWP

8.5

× T

C − 4.5

124.3

—

101.8

—

183 WR assertion to RAS deassertion

tRWL

8.75

× T

C − 4.3

128.3

—

105.1

—

184 WR assertion to CAS deassertion

tCWL

7.75

× T

C − 4.3

113.1

—

92.6

—

185 Data valid to CAS assertion (write)

tDS

4.75

× T

C − 4.0

68.0

—

55.4

—

186 CAS assertion to data not valid (write)

tDH

3.25

× T

C − 4.0

45.2

—

36.6

—

187 RAS assertion to data not valid (write)

tDHR

5.75

× T

C − 4.0

83.1

—

67.9

—

188 WR assertion to CAS assertion

tWCS

5.5

× T

C − 4.3

79.0

—

64.5

—

189 CAS assertion to RAS assertion (refresh)

tCSR

1.5

× T

C − 4.0

18.7

—

14.8

—

190 RAS deassertion to CAS assertion (refresh)

tRPC

1.75

× T

C − 4.0

22.5

—

17.9

—

191 RD assertion to RAS deassertion

tROH

8.5

× T

C − 4.0

124.8

—

102.3

—

192 RD assertion to data valid

tGA

7.5

× T

C − 7.5

7.5

× T

C − 6.5

—

106.1

—

87.3

Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (continued)

No.

Characteristics3

Symbol

Expression4

66 MHz

80 MHz

Unit

Min

Max

Min

Max

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