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DSP56366P датащи(PDF) 40 Page - Freescale Semiconductor, Inc

номер детали DSP56366P
подробное описание детали  24-Bit Audio Digital Signal Processor
PDF  110 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56366P датащи(HTML) 40 Page - Freescale Semiconductor, Inc

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DSP56366 Technical Data, Rev. 3.1
3-14
Freescale Semiconductor
114
WR deassertion time
0.5
× T
C − 4.0
[WS = 1]
0.2
—
ns
TC − 2.0
[2
≤ WS ≤ 3]
6.3
—
ns
2.5
× T
C − 4.0
[4
≤ WS ≤ 7]
16.8
—
ns
3.5
× T
C − 4.0
[WS
≥ 8]
25.2
—
ns
115
Address valid to RD assertion
0.5
× T
C − 4.0
0.2
—
ns
116
RD assertion pulse width
(WS + 0.25)
× T
C −4.0
6.4
—
ns
117
RD deassertion to address not valid
0.25
× T
C − 2.0
[1
≤ WS ≤ 3]
0.1
—
ns
1.25
× T
C − 2.0
[4
≤ WS ≤ 7]
8.4
—
ns
2.25
× T
C − 2.0
[WS
≥ 8]
16.7
—
ns
118
TA setup before RD or WR deassertion4
0.25
× T
C + 2.0
4.1
—
ns
119
TA hold after RD or WR deassertion
0.0
—
ns
1 All timings for 100 MHz are measured from 0.5 · Vcc to .05 · Vcc
2 WS is the number of wait states specified in the BCR.
3 Timings 100, 107 are guaranteed by design, not tested.
4 In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active
Table 3-8 SRAM Read and Write Accesses1 (continued)
No.
Characteristics
Symbol
Expression2
Min
Max
Unit



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