DSP56366P datasheet(57/110 Pages) FREESCALE

57 / 110 page

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-31

Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2

No.

Characteristics3

Symbol

Expression

Min

Max

Unit

157

Random read or write cycle time

tRC

× T

133.3

—

158

RAS assertion to data valid (read)

tRAC

8.25

× T

C − 5.7

—

63.0

159

CAS assertion to data valid (read)

tCAC

4.75

× T

C − 5.7

—

33.9

160

Column address valid to data valid (read)

tAA

5.5

× T

C − 5.7

—

40.1

161

CAS deassertion to data not valid (read hold time)

tOFF

0.0

—

162

RAS deassertion to RAS assertion

tRP

6.25

× T

C − 4.0

48.1

—

163

RAS assertion pulse width

tRAS

9.75

× T

C − 4.0

77.2

—

164

CAS assertion to RAS deassertion

tRSH

6.25

× T

C − 4.0

48.1

—

165

RAS assertion to CAS deassertion

tCSH

8.25

× T

C − 4.0

64.7

—

166

CAS assertion pulse width

tCAS

4.75

× T

C − 4.0

35.6

—

167

RAS assertion to CAS assertion

tRCD

3.5

× T

C ± 2

27.2

31.2

168

RAS assertion to column address valid

tRAD

2.75

× T

C ± 2

20.9

24.9

169

CAS deassertion to RAS assertion

tCRP

7.75

× T

C − 4.0

60.6

—

170

CAS deassertion pulse width

tCP

6.25

× T

C − 4.0

48.1

—

171

Row address valid to RAS assertion

tASR

6.25

× T

C − 4.0

48.1

—

172

RAS assertion to row address not valid

tRAH

2.75

× T

C − 4.0

18.9

—

173

Column address valid to CAS assertion

tASC

0.75

× T

C − 4.0

2.2

—

174

CAS assertion to column address not valid

tCAH

6.25

× T

C − 4.0

48.1

—

175

RAS assertion to column address not valid

tAR

9.75

× T

C − 4.0

77.2

—

176

Column address valid to RAS deassertion

tRAL

× T

C − 4.0

54.3

—

177

WR deassertion to CAS assertion

tRCS

× T

C − 3.8

37.9

—

178

CAS deassertion to WR4 assertion

tRCH

1.75

× T

C − 3.7

10.9

—

179

RAS deassertion to WR5 assertion

tRRH

0.25

× T

C − 2.0

0.1

—

180

CAS assertion to WR deassertion

tWCH

× T

C − 4.2

45.8

—

181

RAS assertion to WR deassertion

tWCR

9.5

× T

C − 4.2

75.0

—

182

WR assertion pulse width

tWP

15.5

× T

C − 4.5

124.7

—

183

WR assertion to RAS deassertion

tRWL

15.75

× T

C − 4.3

126.9

—

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