DSP56366P datasheet(55/110 Pages) FREESCALE

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DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-29

193 RD deassertion to data not valid4

tGZ

0.0

—

0.0

—

194 WR assertion to data active

0.75

× T

C − 0.3

11.1

—

9.1

—

195 WR deassertion to data high impedance

0.25

× T

—3.8

—3.1

1 The number of wait states for out-of-page access is specified in the DCR.

2 The refresh period is specified in the DCR.

3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF and not tGZ.

4 The asynchronous delays specified in the expressions are valid for DSP56366.

5 Either t

RCH or tRRH must be satisfied for read cycles.

Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2

No.

Characteristics3

Symbol

Expression4

Min

Max

Unit

157

Random read or write cycle time

tRC

× T

120.0

—

158

RAS assertion to data valid (read)

tRAC

6.25

× T

C − 7.0

—

55.5

159

CAS assertion to data valid (read)

tCAC

3.75

× T

C − 7.0

—

30.5

160

Column address valid to data valid (read)

tAA

4.5

× T

C − 7.0

—

38.0

161

CAS deassertion to data not valid (read hold time)

tOFF

0.0

—

162

RAS deassertion to RAS assertion

tRP

4.25

× T

C − 4.0

38.5

—

163

RAS assertion pulse width

tRAS

7.75

× T

C − 4.0

73.5

—

164

CAS assertion to RAS deassertion

tRSH

5.25

× T

C − 4.0

48.5

—

165

RAS assertion to CAS deassertion

tCSH

6.25

× T

C − 4.0

58.5

—

166

CAS assertion pulse width

tCAS

3.75

× T

C − 4.0

33.5

—

167

RAS assertion to CAS assertion

tRCD

2.5

× T

C ± 4.0

21.0

29.0

168

RAS assertion to column address valid

tRAD

1.75

× T

C ± 4.0

13.5

21.5

169

CAS deassertion to RAS assertion

tCRP

5.75

× T

C − 4.0

53.5

—

170

CAS deassertion pulse width

tCP

4.25

× T

C − 4.0

38.5

—

171

Row address valid to RAS assertion

tASR

4.25

× T

C − 4.0

38.5

—

172

RAS assertion to row address not valid

tRAH

1.75

× T

C − 4.0

13.5

—

173

Column address valid to CAS assertion

tASC

0.75

× T

C − 4.0

3.5

—

Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (continued)

No.

Characteristics3

Symbol

Expression4

66 MHz

80 MHz

Unit

Min

Max

Min

Max

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