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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DSP56366P датащи(PDF) 44 Page - Freescale Semiconductor, Inc |
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DSP56366P датащи(HTML) 44 Page - Freescale Semiconductor, Inc |
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44 / 110 page  DSP56366 Technical Data, Rev. 3.1 3-18 Freescale Semiconductor 150 CAS assertion to data not valid (write) tDH 0.75 × T C − 4.0 33.5 — 21.0 — ns 151 WR assertion to CAS assertion tWCS TC − 4.3 45.7 — 29.0 — ns 152 Last RD assertion to RAS deassertion tROH 1.5 × T C − 4.0 71.0 — 46.0 — ns 153 RD assertion to data valid tGA TC − 7.5 — 42.5 — 25.8 ns 154 RD deassertion to data not valid6 tGZ 0.0 — 0.0 — ns 155 WR assertion to data active 0.75 × T C − 0.3 37.2 — 24.7 — ns 156 WR deassertion to data high impedance 0.25 × T C — 12.5 — 8.3 ns 1 The number of wait states for Page mode access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t PC equals 2 × TC for read-after-read or write-after-write sequences). 4 Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See Figure 3-14.). 5 BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. 6 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ. Table 3-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 4 No. Characteristics Symbol Expression5 66 MHz 80 MHz Unit Min Max Min Max 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses tPC 2 × T C 1.25 × T C 45.4 41.1 — — 37.5 34.4 — — ns 132 CAS assertion to data valid (read) tCAC 1.5 × T C − 7.5 1.5 × T C − 6.5 — — 15.2 — — — — 12.3 ns ns 133 Column address valid to data valid (read) tAA 2.5 × T C − 7.5 2.5 × T C − 6.5 — — 30.4 — — — — 24.8 ns ns 134 CAS deassertion to data not valid (read hold time) tOFF 0.0 — 0.0 — ns 135 Last CAS assertion to RAS deassertion tRSH 1.75 × T C − 4.0 22.5 — 17.9 — ns 136 Previous CAS deassertion to RAS deassertion tRHCP 3.25 × T C − 4.0 45.2 — 36.6 — ns 137 CAS assertion pulse width tCAS 1.5 × T C − 4.0 18.7 — 14.8 — ns Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 (continued) No. Characteristics Symbol Expression 20 MHz4 30 MHz4 Unit Min Max Min Max |
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