DSP56366P datasheet(58/110 Pages) FREESCALE

номер детали	DSP56366P

подробное описание детали	24-Bit Audio Digital Signal Processor

PDF	110 Pages

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производитель	FREESCALE [Freescale Semiconductor, Inc]

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DSP56366 Technical Data, Rev. 3.1

3-32

Freescale Semiconductor

184

WR assertion to CAS deassertion

tCWL

14.25

× T

C − 4.3

114.4

—

185

Data valid to CAS assertion (write)

tDS

8.75

× T

C − 4.0

68.9

—

186

CAS assertion to data not valid (write)

tDH

6.25

× T

C − 4.0

48.1

—

187

RAS assertion to data not valid (write)

tDHR

9.75

× T

C − 4.0

77.2

—

188

WR assertion to CAS assertion

tWCS

9.5

× T

C − 4.3

74.9

—

189

CAS assertion to RAS assertion (refresh)

tCSR

1.5

× T

C − 4.0

8.5

—

190

RAS deassertion to CAS assertion (refresh)

tRPC

4.75

× T

C − 4.0

35.6

—

191

RD assertion to RAS deassertion

tROH

15.5

× T

C − 4.0

125.2

—

192

RD assertion to data valid

tGA

× T

C − 5.7

—

111.0

193

RD deassertion to data not valid3

tGZ

0.0

—

194

WR assertion to data active

0.75

× T

C − 0.3

5.9

—

195

WR deassertion to data high impedance

0.25

× T

—2.1

1 The number of wait states for out-of-page access is specified in the DCR.

2 The refresh period is specified in the DCR.

3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF and not tGZ.

4 Either t

RCH or tRRH must be satisfied for read cycles.

Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (continued)

No.

Characteristics3

Symbol

Expression

Min

Max

Unit

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