DSP56366P datasheet(47/110 Pages) FREESCALE

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DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-21

150 CAS assertion to data not valid (write)

tDH

2.5

× T

C − 4.0

21.0

—

151 WR assertion to CAS assertion

tWCS

1.25

× T

C − 4.3

8.2

—

152 Last RD assertion to RAS deassertion

tROH

3.5

× T

C − 4.0

31.0

—

153 RD assertion to data valid

tGA

2.5

× T

C − 7.0

—

18.0

154 RD deassertion to data not valid6

tGZ

0.0

—

155 WR assertion to data active

0.75

× T

C − 0.3

7.2

—

156 WR deassertion to data high impedance

0.25

× T

—2.5

1 The number of wait states for Page mode access is specified in the DCR.

2 The refresh period is specified in the DCR.

3 The asynchronous delays specified in the expressions are valid for DSP56366.

4 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t

PC equals 4 × TC for

read-after-read or write-after-write sequences).

5 BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of

page-access.

6 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF and not tGZ.

Table 3-12

DRAM Page Mode Timings, Four Wait States1, 2, 3

No.

Characteristics

Symbol

Expression4

Min

Max

Unit

131

Page mode cycle time for two consecutive accesses of the same

direction.

Page mode cycle time for mixed (read and write) accesses

tPC

× T

4.5

× T

41.7

37.5

—

132

CAS assertion to data valid (read)

tCAC

2.75

× T

C − 7.0

—

15.9

133

Column address valid to data valid (read)

tAA

3.75

× T

C − 7.0

—

24.2

134

CAS deassertion to data not valid (read hold time)

tOFF

0.0

—

135

Last CAS assertion to RAS deassertion

tRSH

3.5

× T

C − 4.0

25.2

—

136

Previous CAS deassertion to RAS deassertion

tRHCP

× T

C − 4.0

46.0

—

137

CAS assertion pulse width

tCAS

2.5

× T

C − 4.0

16.8

—

138

Last CAS deassertion to RAS assertion5

• BRW[1:0] = 00

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

tCRP

2.75

× T

C − 6.0

4.25

× T

C − 6.0

5.25

× T

C − 6.0

7.25

× T

C − 6.0

—

37.7

54.4

—

139

CAS deassertion pulse width

tCP

× T

C − 4.0

12.7

—

Table 3-11

DRAM Page Mode Timings, Three Wait States1, 2, 3 (continued)

No.

Characteristics

Symbol

Expression4

Min

Max

Unit

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