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DSP56366P датащи(PDF) 32 Page - Freescale Semiconductor, Inc |
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DSP56366P датащи(HTML) 32 Page - Freescale Semiconductor, Inc |
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32 / 110 page ![]() DSP56366 Technical Data, Rev. 3.1 3-6 Freescale Semiconductor 3.8 Phase Lock Loop (PLL) Characteristics 3.9 Reset, Stop, Mode Select, and Interrupt Timing 4 EXTAL cycle time2 • With PLL disabled • With PLL enabled ETC 8.33 ns 8.33 ns ∞ 273.1 μs 7 Instruction cycle time = ICYC = TC 4, 2 • With PLL disabled • With PLL enabled ICYC 16.66 ns 8.33 ns ∞ 8.53 μs 1 Measured at 50% of the input transition. 2 The maximum value for PLL enabled is given for minimum V CO and maximum MF. 3 The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. 4 The maximum value for PLL enabled is given for minimum VCO and maximum DF. Table 3-6 PLL Characteristics Characteristics Min Max Unit VCO frequency when PLL enabled (MF × Ef × 2/PDF) 30 240 MHz PLL external capacitor (PCAP pin to VCCP) (CPCAP) 1 • @ MF ≤ 4 • @ MF > 4 1 CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for CPCAP can be computed from one of the following equations: (MF x 680)-120, for MF ≤ 4 or MF x 1100, for MF > 4. (MF × 580) − 100 MF × 830 (MF × 780) − 140 MF × 1470 pF Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1 No. Characteristics Expression Min Max Unit 8 Delay from RESET assertion to all pins at reset value2 — — 26.0 ns 9 Required RESET duration3 • Power on, external clock generator, PLL disabled • Power on, external clock generator, PLL enabled • During normal operation 50 × ET C 1000 × ET C 2.5 × T C 416.7 8.3 20.8 — — — ns μs ns 10 Delay from asynchronous RESET deassertion to first external address output (internal reset deassertion)4 •Minimum • Maximum 3.25 × T C + 2.0 20.25 TC + 7.50 29.1 — — 176.2 ns ns 13 Mode select setup time 30.0 — ns Table 3-5 Clock Operation (continued) No. Characteristics Symbol Min Max |
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