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DSP56366P датащи(PDF) 61 Page - Freescale Semiconductor, Inc |
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DSP56366P датащи(HTML) 61 Page - Freescale Semiconductor, Inc |
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61 / 110 page ![]() DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor 3-35 Figure 3-17 DRAM Refresh Access 3.10.3 Arbitration Timings Table 3-17 Asynchronous Bus Arbitration timing No. Characteristics Expression 120 MHz Unit Min Max 250 BB assertion window from BG input negation. 2 .5* Tc + 5 — 25.8 ns 251 Delay from BB assertion to BG assertion 2 * Tc + 5 21.7 — ns Notes: 1. Bit 13 in the OMR register must be set to enter Asynchronous Arbitration mode 2. If Asynchronous Arbitration mode is active, none of the timings in Table 3-17 is required. 3. In order to guarantee timings 250, and 251, it is recommended to assert BG inputs to different 56300 devices (on the same bus) in a non overlap manner as shown in Figure 3-18. RAS CAS WR 157 163 162 162 190 170 165 189 177 AA0478 |
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