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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DSP56366P датащи(PDF) 31 Page - Freescale Semiconductor, Inc |
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DSP56366P датащи(HTML) 31 Page - Freescale Semiconductor, Inc |
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31 / 110 page  DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor 3-5 3.7 EXTERNAL CLOCK OPERATION The DSP56366 system clock is an externally supplied square wave voltage source connected to EXTAL (See Figure 3-1). Figure 3-1 External Clock Timing Internal clock cycle time with PLL disabled TC —2 × ET C — Instruction cycle time ICYC —TC — 1 DF = Division Factor Ef = External frequency ETC = External clock cycle MF = Multiplication Factor PDF = Predivision Factor TC = internal clock cycle 2 See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion of the PLL. Table 3-5 Clock Operation No. Characteristics Symbol Min Max 1 Frequency of EXTAL (EXTAL Pin Frequency) The rise and fall time of this external clock should be 3 ns maximum. Ef 0 120.0 2 EXTAL input high1, 2 • With PLL disabled (46.7%–53.3% duty cycle3) • With PLL enabled (42.5%–57.5% duty cycle3) ETH 3.89 ns 3.54 ns ∞ 157.0 μs 3 EXTAL input low1, 2 • With PLL disabled (46.7%–53.3% duty cycle3) • With PLL enabled (42.5%–57.5% duty cycle3) ETL 3.89 ns 3.54 ns ∞ 157.0 μs Table 3-4 Internal Clocks Characteristics Symbol Expression1, 2 Min Typ Max EXTAL VILC VIHC Midpoint Notes The midpoint is 0.5 (VIHC + VILC). ETH ETL ETC 3 4 2 |
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