DSP56366P datasheet(56/110 Pages) FREESCALE

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DSP56366 Technical Data, Rev. 3.1

3-30

Freescale Semiconductor

174

CAS assertion to column address not valid

tCAH

5.25

× T

C − 4.0

48.5

—

175

RAS assertion to column address not valid

tAR

7.75

× T

C − 4.0

73.5

—

176

Column address valid to RAS deassertion

tRAL

× T

C − 4.0

56.0

—

177

WR deassertion to CAS assertion

tRCS

3.0

× T

C − 4.0

26.0

—

178

CAS deassertion to WR5 assertion

tRCH

1.75

× T

C − 4.0

13.5

—

179

RAS deassertion to WR5 assertion

tRRH

0.25

× T

C − 2.0

0.5

—

180

CAS assertion to WR deassertion

tWCH

× T

C − 4.2

45.8

—

181

RAS assertion to WR deassertion

tWCR

7.5

× T

C − 4.2

70.8

—

182

WR assertion pulse width

tWP

11.5

× T

C − 4.5

110.5

—

183

WR assertion to RAS deassertion

tRWL

11.75

× T

C − 4.3

113.2

—

184

WR assertion to CAS deassertion

tCWL

10.25

× T

C − 4.3

103.2

—

185

Data valid to CAS assertion (write)

tDS

5.75

× T

C − 4.0

53.5

—

186

CAS assertion to data not valid (write)

tDH

5.25

× T

C − 4.0

48.5

—

187

RAS assertion to data not valid (write)

tDHR

7.75

× T

C − 4.0

73.5

—

188

WR assertion to CAS assertion

tWCS

6.5

× T

C − 4.3

60.7

—

189

CAS assertion to RAS assertion (refresh)

tCSR

1.5

× T

C − 4.0

11.0

—

190

RAS deassertion to CAS assertion (refresh)

tRPC

2.75

× T

C − 4.0

23.5

—

191

RD assertion to RAS deassertion

tROH

11.5

× T

C − 4.0

111.0

—

192

RD assertion to data valid

tGA

× T

C − 7.0

—

93.0

193

RD deassertion to data not valid3

tGZ

0.0

—

194

WR assertion to data active

0.75

× T

C − 0.3

7.2

—

195

WR deassertion to data high impedance

0.25

× T

—2.5

1 The number of wait states for out-of-page access is specified in the DCR.

2 The refresh period is specified in the DCR.

3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF and not tGZ.

4 The asynchronous delays specified in the expressions are valid for DSP56366.

5 Either t

RCH or tRRH must be satisfied for read cycles.

Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (continued)

No.

Characteristics3

Symbol

Expression4

Min

Max

Unit

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