AM62A7 datasheet(203/238 Pages) TI1

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Table 7-123. OSPI0 Switching Characteristics – Tap DDR Mode

see Figure 7-106

NO.

PARAMETER

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI0_CLK

tw(CLKL)

Pulse duration, OSPI0_CLK low

((0.475P(1)) - 0.3)

tw(CLKH)

Pulse duration, OSPI0_CLK high

((0.475P(1)) - 0.3)

td(CSn-CLK)

Delay time, OSPI0_CSn[3:0] active edge

to OSPI0_CLK rising edge

((0.475P(1)) +

((0.975M(2)R(5)) - 1)

((0.525P(1)) +

( 1.025M(2)R(5)) + 1)

td(CLK-CSn)

Delay time, OSPI0_CLK rising edge to

OSPI0_CSn[3:0] inactive edge

((0.475P(1)) +

(0.975N(3)R(5)) - 1)

((0.525P(1)) +

(1.025N(3)R(5)) + 1)

td(CLK-D)

Delay time, OSPI0_CLK active edge to

OSPI0_D[7:0] transition

(- 5.04 +

(0.975(T(4) + 1)R(5))

- (0.525P(1)))

(3.64 +

(1.025(T(4) + 1)R(5))

- (0.475P(1)))

(1)

P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns

(2)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

T = OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD]

(5)

R = reference clock cycle time in ns

OSPI_CLK

OSPI_TIMING_01

OSPI_CSn

OSPI_D[i:0]

Figure 7-106. OSPI0 Switching Characteristics – Tap DDR, No Loopback

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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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