AM62A7 datasheet(185/238 Pages) TI1

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7.10.5.16.2.2 High Speed Mode

Table 7-101, Figure 7-85, Table 7-102, and Figure 7-86 present timing requirements and switching

characteristics for MMC1/MMC2 – High Speed Mode.

Table 7-101. Timing Requirements for MMC1/MMC2 – High Speed Mode

see Figure 7-85

NO.

MIN

MAX

UNIT

HS1

tsu(cmdV-clkH)

Setup time, MMCx_CMD valid before MMCx_CLK rising edge

2.24

HS2

th(clkH-cmdV)

Hold time, MMCx_CMD valid after MMCx_CLK rising edge

1.66

HS3

tsu(dV-clkH)

Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge

2.24

HS4

th(clkH-dV)

Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge

1.66

MMC[ ]_CLK

MMC[ ]_CMD

MMC

DAT

[ ]_

[3:0]

H 1

H 2

H 3

H 4

Figure 7-85. MMC1/MMC2 – High Speed – Receive Mode

Table 7-102. Switching Characteristics for MMC1/MMC2 – High Speed Mode

see Figure 7-86

NO.

PARAMETER

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMCx_CLK

MHz

HS5

tc(clk)

Cycle time. MMCx_CLK

HS6

tw(clkH)

Pulse duration, MMCx_CLK high

9.2

HS7

tw(clkL)

Pulse duration, MMCx_CLK low

9.2

HS8

td(clkL-cmdV)

Delay time, MMCx_CLK falling edge to MMCx_CMD transition

- 1.8

2.2

HS9

td(clkL-dV)

Delay time, MMCx_CLK falling edge to MMCx_DAT[3:0] transition

- 1.8

2.2

MMC[x]_CLK

MMC

CMD

[ ]_

MMC

DAT

[ ]_

[3:0]

H 5

H 7

H 8

H 9

HS6

Figure 7-86. MMC1/MMC2 – High Speed – Transmit Mode

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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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