IMX7DCEC datasheet(115/161 Pages) NXP

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

115

4.10.14.2.1 UART transmitter

Figure 83 depicts the transmit timing of UART in the RS-232 Serial mode, with 8 data bit/1 stop bit

format. Table 89 lists the UART RS-232 Serial mode transmit timing characteristics.

Figure 83. UART RS-232 Serial mode transmit timing diagram

4.10.14.2.2 UART receiver

Figure 84 depicts the RS-232 Serial mode receive timing with 8 data bit/1 stop bit format. Table 90 lists

Serial mode receive timing characteristics.

Figure 84. UART RS-232 Serial mode receive timing diagram

4.10.15 USB HSIC timing

This section describes the electrical information of the USB HSIC port.

Table 89. RS-232 Serial mode transmit timing parameters

Parameter

Symbol

Min

Max

Unit

UA1 Transmit Bit Time

tTbit

1/Fbaud_rate1 - Tref_clk2

1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

2 Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

1/Fbaud_rate + Tref_clk

—

Table 90. RS-232 Serial mode receive timing parameters

Parameter

Symbol

Min

Max

Unit

UA2

Receive Bit Time1

1 The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not

exceed 3/(16 x Fbaud_rate).

tRbit

1/Fbaud_rate2 - 1/(16

x Fbaud_rate)

2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

1/Fbaud_rate +

1/(16 x Fbaud_rate)

—

Start

Bit

Bit 1

Bit 2

Bit 0

Bit 4

Bit 5

Bit 6

Bit 7

UARTx_TX_DATA

(output)

Bit 3

STOP

BIT

Start

Bit

Possible

Parity

Bit

Par Bit

UA1

Bit 1

Bit 2

Bit 0

Bit 4

Bit 5

Bit 6

Bit 7

UARTx_RX_DATA

(output)

Bit 3

Start

Bit

STOP

BIT

Start

Bit

Possible

Parity

Bit

Par Bit

UA2

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