IMX7DCEC datasheet(14/161 Pages) NXP

14 / 161 page

Modules list

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

SJC

System JTAG Controller

System control

peripherals

The SJC provides JTAG interface (designed to be

compatible with JTAG TAP standards) to internal logic.

The i.MX 7Dual family of processors uses JTAG port for

production, testing, and system debugging.

Additionally, the SJC provides BSR (Boundary Scan

with IEEE 1149.1 and IEEE1149.6 standards.

The JTAG port must be accessible during platform

initial laboratory bring-up, for manufacturing tests and

troubleshooting, as well as for software debugging by

authorized entities. The i.MX 7Dual SJC incorporates

three security modes for protecting against

unauthorized accesses. Modes are selected through

eFUSE configuration.

SNVS

Secure Non-Volatile

Storage

Security

Secure Non-Volatile Storage, including Secure Real

Time Clock, Security State Machine, Master Key

Control, and Violation/Tamper Detection and reporting.

TEMPSENSOR

Temperature Sensor

System control

peripherals

Temperature sensor

TZASC

Trust-Zone Address

Space Controller

Security

The TZASC (TZC-380 by Arm) provides security

address region control functions required for intended

application. It is used on the path to the DRAM

controller.

UART1

UART2

UART3

UART4

UART5

UART6

UART7

UART Interface

Connectivity

peripherals

Each of the UARTv2 modules support the following

serial data transmit/receive protocols and

configurations:

• 7- or 8-bit data words, 1 or 2 stop bits, programmable

parity (even, odd or none)

• Programmable baud rates up to 4 Mbps. This is a

higher max baud rate relative to the 1.875 MHz,

which is stated by the TIA/EIA-232-F standard.

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx

supporting auto-baud

Table 2. i.MX 7Dual modules list(continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

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