IMX7DCEC datasheet(31/161 Pages) NXP

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

When LPSR mode is not needed for the application, the VDD_LPSR can be connected to VDDA_1P8 and

NVCC_GPIO1/2 can be connected to the same power supply as NVCC_XXX for other GPIO banks.

In LPSR mode, the supported wakeup source are RTC alarm, ONOFF event, security/tamper and also the

16 GPIO pads.

4.1.6.4

RUN Mode

In RUN mode, the CPU is active and running, and the analog / digital peripheral modules inside the

processor will be enabled. In this mode, all the external power rails to the processor have to be ON and the

SoC will be able to draw as many current as listed in the Table 5 Maximum Power Requirement.

In this mode, the PMIC should allow SoC to change the voltage of power rails through I2C/SPI interface.

Typically, when the CPU is doing DVFS, it switches the VDD_ARM voltage according to Table 9 when

the CPU’s frequency is switching between 1 GHz and 800 MHz (or below).

4.1.6.5

Low Power Mode

When the CPU is not running, the processor can enter low power mode. i.MX 7Dual processor supports a

very flexible set of power mode configurations in low power mode.

Typically there are 3 low power modes used, System IDLE, Low Power IDLE and SUSPEND:

• System IDLE—This is a mode that the CPU can automatically enter when there is no thread

running. All the peripherals can keep working and the CPU’s state is retained so the interrupt

response can be very short. The cores are able to individually enter the WAIT state.

• Low Power IDLE—This mode is for the case when the system needs to have lower power but still

keep some of the peripherals alive. Most of the peripherals, analog modules, and PHYs are shut

off; see Table 5-5, “Low Power Mode Definition,” in the i.MX 7Dual Application Processor

Reference Manual (IMX7DRM) for details. The interrupt response in this mode is expected to be

longer than the System IDLE, but its power is much lower.

• Suspend—This mode has the greatest power savings; all clocks, unused analog/PHYs, and

peripherals are off. The external DRAM stays in Self-Refresh mode. The exit time from this mode

is much longer.

In System IDLE and Low Power IDLE mode, the voltage on external power supplies remains the same as

in RUN mode, so the external PMIC is not aware of the state of the processor. If any low-power setting

needs to be applied to PMIC, it is done through the I2C/SPI interface before the processor enters a

low-power mode.

When the processor enters SUSPEND mode, it will assert the PMIC_STBY_REQ signal to PMIC. When

this signal is asserted, the processor allows the PMIC to shut off VDD_ARM externally. However, in some

application scenario, SW want to keep the data in L2 Cache to avoid performance impact on cache miss.

In this case, the VDD_ARM cannot be shut off. To support both scenarios, the PMIC should have an option

to shut off or keep VDD_ARM when it receives the PMIC_STBY_REQ. This should be configured

through I2C/SPI interface before the processor enters SUSPEND mode.

Except the VDD_ARM, the other power rails have to keep active in SUSPEND mode. Since the current

on each power rail is greatly reduced in this mode, PMIC can enter its own low power mode to get extra

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