IMX7DCEC datasheet(41/161 Pages) NXP

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

4.2.1

Internal regulators

4.2.1.1

LDO_1P2

The LDO_1P2 regulator implements a programmable linear-regulator function from VDDA_1P8_IN (see

Table 9 for minimum and maximum input requirements). The typical output of the LDO, VDD_1P2_CAP,

is 1.2 V. It is intended for use with the USB HSIC PHY, which uses this voltage level for its output driver.

For additional information, see the “Power Management Unit (PMU)” chapter of the i.MX 7Dual

Application Processor Reference Manual (IMX7DRM).

4.2.1.2

LDO_1P0D

The LDO_1P0D regulator implements a programmable linear-regulator function from VDDA_1P8_IN

(see Table 9 for minimum and maximum input requirements). The typical output of the LDO,

VDD_1P0D_CAP, is 1.0 V. It is intended for use with the internal physical interfaces, including MIPI and

PCIe PHY. For additional information, see the i.MX 7Dual Application Processor Reference Manual

(IMX7DRM).

4.2.1.3

LDO_1P0A

The LDO_1P0A regulator implements a programmable linear-regulator function from VDDA_1P8_IN

(see Table 9 for minimum and maximum input requirements). The typical output of the LDO,

VDD_1P0A_CAP, is 1.0 V. It is intended for use with the internal analog modules, including the XTAL,

ADC, PLL, and Temperature Sensor. For additional information, see the i.MX 7Dual Application

Processor Reference Manual (IMX7DRM).

4.2.1.4

LDO_USB1_1PO/LDO_USB2_1P0

The LDO_USB1_1P0/LDO_USB2_1P0 regulators implement a fixed linear-regulator function from

VDD_USB_OTG1_3P3_IN and VDD_USB_OTG2_3P3_IN power inputs respectively (see Table 9 for

minimum and maximum input requirements). The typical output voltage is 1.0 V. It is intended for use

with the internal USB physical interfaces (USB PHY1 and USB PHY2). For additional information, see

the i.MX 7Dual Application Processor Reference Manual (IMX7DRM).

Table 26. LDO parameters

Parameter

Min

Max

Units

PVCC_GPIO_AT3P3_1P8

1.6

1.98

VDD_1P2

1.1

1.32

LPSR_1P0

0.95

1.155

VDDA_PHY_1P8

1.6

1.98

USB_OTG1_1P0

0.95

1.155

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