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IMX7DCEC датащи(PDF) 66 Page - NXP Semiconductors

номер детали IMX7DCEC
подробное описание детали  i.MX 7Dual Family of Applications Processors Datasheet
PDF  161 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

IMX7DCEC датащи(HTML) 66 Page - NXP Semiconductors

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Electrical characteristics
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023
NXP Semiconductors
66
4.8.4
DDR SDRAM-specific parameters (DDR3, DDR3L, LPDDR3, and
LPDDR2)
4.8.4.1
DDR3/DDR3L parameters
Figure 24 shows the DDR3 basic timing diagram with the timing parameters provided in Table 47.
Figure 24. DDR3 Command and Address Timing Diagram
Table 47. DDR3 timing parameters
ID
Parameter
Symbol
CK = 533 MHz
Unit
Min
Max
DDR1 DRAM_SDCLKx_P clock high-level width
tCH
0.47
0.53
tCK
DDR2 DRAM_SDCLKx_P clock low-level width
tCL
0.47
0.53
tCK
DDR4 DRAM_CSx_B, DRAM_RAS_B, DRAM_CAS_B, DRAM_SDCKE, DRAM_SDWE_B,
DRAM_SDODTx setup time
tIS
425
—
ps
DDR5 DRAM_CSx_B, DRAM_RAS_B, DRAM_CAS_B, DRAM_SDCKE, DRAM_SDWE_B,
DRAM_SDODTx hold time
tIH
375
—
ps
DDR6 Address output setup time
tIS
425
—
ps
DDR7 Address output hold time
tIH
375
—
ps
DRAM_SDWE_B
DRAM_ADDRxx
ROW/BA
COL/BA
DDR1
DDR2
DDR4
DDR4
DDR5
DDR5
DDR5
DDR5
DDR6
DDR7
DRAM_SDCLKx_P
DRAM_ODTx /
DDR4
DRAM_SDCKEx
DRAM_SDCLKx_N
DRAM_CSx_B
DRAM_RAS_B
DRAM_CAS_B
DDR4



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