IMX7DCEC datasheet(7/161 Pages) NXP

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i.MX 7Dual introduction

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

The i.MX 7Dual family of processors integrates advanced power management unit and controllers:

• PMU (power-management unit), multiple LDO supplies, for on-chip resources

• Temperature sensor for monitoring the die temperature

• Software state retention and power gating for Arm and NEON

• Support for various levels of system power modes

• Flexible clock gating control scheme

The i.MX 7Dual family of processors uses dedicated hardware accelerators to meet the targeted

multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance

at low power consumption numbers, while having the CPU core relatively free for performing other tasks.

The i.MX 7Dual family of processors incorporates the following hardware accelerators:

• PXP—PiXel processing pipeline for imagine resize, rotation, overlay and CSC. Off loading key

pixel processing operations are required to support the LCD and EPDC display applications.

• EPDC—Low-power, high-performance, direct-drive, active-matrix electrophoretic display

controller, specifically designed to drive E Ink EPD panels.

Security functions are implemented by the following hardware:

• Arm TrustZone technology including separation of interrupts and memory mapping

• SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or

blocking the access to the system debug features.

• CAAM—Cryptographic Acceleration and Assurance Module, containing cryptographic and hash

engines, 32 KB secure RAM, and true and pseudo random number generator.

• SNVS—Secure Non-Volatile Storage, including secure real time clock

• CSU—Central Security Unit. Responsible for setting comprehensive security policy of the device.

Configured during boot and by eFuses and determines the security-level operation mode as well as

the TrustZone policy.

• HAB—High Assurance Boot—HABv4 with the new embedded enhancements: SHA-256,

2048-bit RSA key, SRK revocation mechanism, warm boot, CSU, and TrustZone initialization.

NOTE

The actual feature set depends on the part numbers as described in Table 1.

Functions, such as display and camera interfaces, connectivity interfaces,

may not be enabled for specific part numbers.

IMX7DCEC датащи(PDF) 7 Page - NXP Semiconductors