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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX7DCEC датащи(PDF) 69 Page - NXP Semiconductors |
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IMX7DCEC датащи(HTML) 69 Page - NXP Semiconductors |
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69 / 161 page  Electrical characteristics i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023 NXP Semiconductors 69 Figure 28 shows the LPDDR3 write timing diagram. The timing parameters for this diagram appear in Table 51. Figure 28. LPDDR3 write cycle Table 50. LPDDR3 timing parameters1,2 1 All measurements are in reference to Vref level. 2 Measurements were done using balanced load and 25 resistor from outputs to DDR_VREF. ID Parameter Symbol CK = 533 MHz Unit Min Max LP1 SDRAM clock high-level width tCH 0.45 0.55 tCK LP2 SDRAM clock low-level width tCL 0.45 0.55 tCK LP3 DRAM_CSx_B tIS 390 — ps LP4 DRAM_CSx_E tIH 390 — ps LP3 DRAM_CAS_B setup time tIS 275 — ps LP4 DRAM_CAS_B hold time tIH 275 — ps |
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